From efdfacd31d2d9f492e28cafecb62c20c26361c0d Mon Sep 17 00:00:00 2001 From: Chen Qun Date: Wed, 16 Sep 2020 19:40:28 +0800 Subject: [PATCH] target/arm: only set ID_PFR1_EL1.GIC for AArch32 guest Some AArch64 CPU doesn't support AArch32 mode, and the values of AArch32 registers are all 0. Hence, We'd better not to modify AArch32 registers in AArch64 mode. Signed-off-by: zhanghailiang Signed-off-by: Peng Liang Signed-off-by: Dongxu Sun --- ...set-ID_PFR1_EL1.GIC-for-AArch32-gues.patch | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 target-arm-only-set-ID_PFR1_EL1.GIC-for-AArch32-gues.patch diff --git a/target-arm-only-set-ID_PFR1_EL1.GIC-for-AArch32-gues.patch b/target-arm-only-set-ID_PFR1_EL1.GIC-for-AArch32-gues.patch new file mode 100644 index 0000000..a9be076 --- /dev/null +++ b/target-arm-only-set-ID_PFR1_EL1.GIC-for-AArch32-gues.patch @@ -0,0 +1,32 @@ +From 3371917ea92265377f87692a717397267416c4aa Mon Sep 17 00:00:00 2001 +From: Peng Liang +Date: Wed, 16 Sep 2020 19:40:28 +0800 +Subject: [PATCH] target/arm: only set ID_PFR1_EL1.GIC for AArch32 guest + +Some AArch64 CPU doesn't support AArch32 mode, and the values of AArch32 +registers are all 0. Hence, We'd better not to modify AArch32 registers +in AArch64 mode. + +Signed-off-by: zhanghailiang +Signed-off-by: Peng Liang +Signed-off-by: Dongxu Sun +--- + target/arm/helper.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/target/arm/helper.c b/target/arm/helper.c +index 79f77705c3..4c7b4cadfa 100644 +--- a/target/arm/helper.c ++++ b/target/arm/helper.c +@@ -6718,7 +6718,7 @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) + ARMCPU *cpu = env_archcpu(env); + uint64_t pfr1 = cpu->isar.regs[ID_PFR1]; + +- if (env->gicv3state) { ++ if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && env->gicv3state) { + pfr1 |= 1 << 28; + } + return pfr1; +-- +2.27.0 +