From e40499de244d5ac7eb0431f9b830ce0bd4db65ac Mon Sep 17 00:00:00 2001 From: Yan Wang Date: Sat, 26 Feb 2022 11:13:19 +0800 Subject: [PATCH] pcie: Compat with devices which do not support Link Width, such as ioh3420 We hack into PCI_EXP_LNKCAP to support device fast plug/unplug for pcie-root-port. However some devices like ioh3420 does not suport it, so PCI_EXP_LNKCAP is not set for such devices. Signed-off-by: Ying Fang Signed-off-by: Yan Wang --- ...-devices-which-do-not-support-Link-W.patch | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 pcie-Compat-with-devices-which-do-not-support-Link-W.patch diff --git a/pcie-Compat-with-devices-which-do-not-support-Link-W.patch b/pcie-Compat-with-devices-which-do-not-support-Link-W.patch new file mode 100644 index 0000000..aeb31bb --- /dev/null +++ b/pcie-Compat-with-devices-which-do-not-support-Link-W.patch @@ -0,0 +1,50 @@ +From 14d1ad1309a1bd035250512368221088c2f83f32 Mon Sep 17 00:00:00 2001 +From: fangying +Date: Wed, 18 Mar 2020 12:51:33 +0800 +Subject: [PATCH 6/6] pcie: Compat with devices which do not support Link + Width, such as ioh3420 + +We hack into PCI_EXP_LNKCAP to support device fast plug/unplug +for pcie-root-port. However some devices like ioh3420 does not +suport it, so PCI_EXP_LNKCAP is not set for such devices. + +Signed-off-by: Ying Fang +Signed-off-by: Yan Wang +--- + hw/pci/pcie.c | 13 ++++++------- + 1 file changed, 6 insertions(+), 7 deletions(-) + +diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c +index d7d1504..30c09ed 100644 +--- a/hw/pci/pcie.c ++++ b/hw/pci/pcie.c +@@ -92,13 +92,6 @@ static void pcie_cap_fill_slot_lnk(PCIDevice *dev) + return; + } + +- /* Clear and fill LNKCAP from what was configured above */ +- pci_long_test_and_clear_mask(exp_cap + PCI_EXP_LNKCAP, +- PCI_EXP_LNKCAP_MLW | PCI_EXP_LNKCAP_SLS); +- pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP, +- QEMU_PCI_EXP_LNKCAP_MLW(s->width) | +- QEMU_PCI_EXP_LNKCAP_MLS(s->speed)); +- + /* + * Link bandwidth notification is required for all root ports and + * downstream ports supporting links wider than x1 or multiple link +@@ -106,6 +99,12 @@ static void pcie_cap_fill_slot_lnk(PCIDevice *dev) + */ + if (s->width > QEMU_PCI_EXP_LNK_X1 || + s->speed > QEMU_PCI_EXP_LNK_2_5GT) { ++ /* Clear and fill LNKCAP from what was configured above */ ++ pci_long_test_and_clear_mask(exp_cap + PCI_EXP_LNKCAP, ++ PCI_EXP_LNKCAP_MLW | PCI_EXP_LNKCAP_SLS); ++ pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP, ++ QEMU_PCI_EXP_LNKCAP_MLW(s->width) | ++ QEMU_PCI_EXP_LNKCAP_MLS(s->speed)); + pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP, + PCI_EXP_LNKCAP_LBNC); + } +-- +1.9.1 +