From dadccf364631b178ba926934a372735bafadd9c8 Mon Sep 17 00:00:00 2001 From: Chen Qun Date: Tue, 20 Jul 2021 16:27:34 +0800 Subject: [PATCH] spec: Update patch and changelog with !161 x86: new CPU models for Denverton (server-class Atom-based SoC), Snowridge, and Dhyana !161 target/i386: Introduce Denverton CPU model target/i386: Add Snowridge-v2 (no MPX) CPU model i386: Add CPUID bit for CLZERO and XSAVEERPTR Signed-off-by: Chen Qun --- qemu.spec | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qemu.spec b/qemu.spec index 23a9ced..ca424ab 100644 --- a/qemu.spec +++ b/qemu.spec @@ -346,6 +346,9 @@ Patch0333: target-i386-Add-new-bit-definitions-of-MSR_IA32_ARCH.patch Patch0334: target-i386-Add-missed-security-features-to-Cooperla.patch Patch0335: target-i386-add-PSCHANGE_NO-bit-for-the-ARCH_CAPABIL.patch Patch0336: target-i386-Export-TAA_NO-bit-to-guests.patch +Patch0337: target-i386-Introduce-Denverton-CPU-model.patch +Patch0338: target-i386-Add-Snowridge-v2-no-MPX-CPU-model.patch +Patch0339: i386-Add-CPUID-bit-for-CLZERO-and-XSAVEERPTR.patch BuildRequires: flex BuildRequires: gcc @@ -740,6 +743,11 @@ getent passwd qemu >/dev/null || \ %endif %changelog +* Tue Jul 20 2021 Chen Qun +- target/i386: Introduce Denverton CPU model +- target/i386: Add Snowridge-v2 (no MPX) CPU model +- i386: Add CPUID bit for CLZERO and XSAVEERPTR + * Mon Jul 19 2021 Chen Qun - x86: Intel AVX512_BF16 feature enabling - i386: Add MSR feature bit for MDS-NO