diff --git a/target-arm-Add-more-CPU-features.patch b/target-arm-Add-more-CPU-features.patch
new file mode 100644
index 0000000..4b8c01d
--- /dev/null
+++ b/target-arm-Add-more-CPU-features.patch
@@ -0,0 +1,31 @@
+From 85d5b46d8225c5875b8b3ff68967d46bcde9a549 Mon Sep 17 00:00:00 2001
+From: Peng Liang <liangpeng10@huawei.com>
+Date: Tue, 11 Aug 2020 10:28:10 +0800
+Subject: [PATCH] target/arm: Add more CPU features
+
+Add i8mm, bf16, and dgh CPU features for AArch64.
+
+Signed-off-by: zhanghailiang <zhang.zhanghailiang@huawei.com>
+Signed-off-by: Peng Liang <liangpeng10@huawei.com>
+Signed-off-by: Dongxu Sun <sundongxu3@huawei.com>
+---
+ target/arm/cpu.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/target/arm/cpu.c b/target/arm/cpu.c
+index 2d6a26336f..1c1647a0a8 100644
+--- a/target/arm/cpu.c
++++ b/target/arm/cpu.c
+@@ -1309,6 +1309,9 @@ static struct CPUFeatureInfo cpu_features[] = {
+     FIELD_INFO("fhm", ID_ISAR6, FHM, false, 1, 0, true),
+     FIELD_INFO("sb", ID_ISAR6, SB, false, 1, 0, true),
+     FIELD_INFO("specres", ID_ISAR6, SPECRES, false, 1, 0, true),
++    FIELD_INFO("i8mm", ID_AA64ISAR1, I8MM, false, 1, 0, false),
++    FIELD_INFO("bf16", ID_AA64ISAR1, BF16, false, 1, 0, false),
++    FIELD_INFO("dgh", ID_AA64ISAR1, DGH, false, 1, 0, false),
+ 
+     FIELD_INFO("cmaintva", ID_MMFR3, CMAINTVA, false, 1, 0, true),
+     FIELD_INFO("cmaintsw", ID_MMFR3, CMAINTSW, false, 1, 0, true),
+-- 
+2.27.0
+