diff --git a/target-arm-Update-the-ID-registers-of-Kunpeng-920.patch b/target-arm-Update-the-ID-registers-of-Kunpeng-920.patch
new file mode 100644
index 0000000..b632a31
--- /dev/null
+++ b/target-arm-Update-the-ID-registers-of-Kunpeng-920.patch
@@ -0,0 +1,58 @@
+From e2cb8b57278357c0a42cf7722b8c28b6f8d7585c Mon Sep 17 00:00:00 2001
+From: Peng Liang <liangpeng10@huawei.com>
+Date: Sat, 19 Sep 2020 09:04:45 +0800
+Subject: [PATCH] target/arm: Update the ID registers of Kunpeng-920
+
+The values of some ID registers in Kunpeng-920 are not exactly correct.
+Let's update them.  The values are read from Kunpeng-920 by calling
+read_sysreg_s.
+
+Signed-off-by: Peng Liang <liangpeng10@huawei.com>
+Signed-off-by: Dongxu Sun <sundongxu3@huawei.com>
+---
+ target/arm/cpu64.c | 27 +++++++++++++++++++++++++--
+ 1 file changed, 25 insertions(+), 2 deletions(-)
+
+diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
+index 287e7ac91c..3ec788fc29 100644
+--- a/target/arm/cpu64.c
++++ b/target/arm/cpu64.c
+@@ -262,10 +262,33 @@ static void aarch64_kunpeng_920_initfn(Object *obj)
+ 
+     cpu->midr = 0x480fd010;
+     cpu->ctr = 0x84448004;
+-    cpu->isar.regs[ID_AA64PFR0] = 0x11001111;
++    cpu->isar.regs[ID_ISAR0] = 0;
++    cpu->isar.regs[ID_ISAR1] = 0;
++    cpu->isar.regs[ID_ISAR2] = 0;
++    cpu->isar.regs[ID_ISAR3] = 0;
++    cpu->isar.regs[ID_ISAR4] = 0;
++    cpu->isar.regs[ID_ISAR5] = 0;
++    cpu->isar.regs[ID_MMFR0] = 0;
++    cpu->isar.regs[ID_MMFR1] = 0;
++    cpu->isar.regs[ID_MMFR2] = 0;
++    cpu->isar.regs[ID_MMFR3] = 0;
++    cpu->isar.regs[ID_MMFR4] = 0;
++    cpu->isar.regs[MVFR0] = 0;
++    cpu->isar.regs[MVFR1] = 0;
++    cpu->isar.regs[MVFR2] = 0;
++    cpu->isar.regs[ID_DFR0] = 0;
++    cpu->isar.regs[MVFR2] = 0;
++    cpu->isar.regs[MVFR2] = 0;
++    cpu->isar.regs[MVFR2] = 0;
++    cpu->isar.regs[ID_PFR0] = 0;
++    cpu->isar.regs[ID_PFR1] = 0;
++    cpu->isar.regs[ID_AA64PFR0] = 0x0000010011111111;
+     cpu->isar.regs[ID_AA64DFR0] = 0x110305408;
+-    cpu->isar.regs[ID_AA64ISAR0] = 0x10211120;
++    cpu->isar.regs[ID_AA64ISAR0] = 0x0001100010211120;
++    cpu->isar.regs[ID_AA64ISAR1] = 0x00011001;
+     cpu->isar.regs[ID_AA64MMFR0] = 0x101125;
++    cpu->isar.regs[ID_AA64MMFR1] = 0x10211122;
++    cpu->isar.regs[ID_AA64MMFR2] = 0x00001011;
+ }
+ 
+ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
+-- 
+2.27.0
+