52 lines
1.9 KiB
Diff
52 lines
1.9 KiB
Diff
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From 2c6cf54ea2f52774f2587e7e66eed9beba3a3dec Mon Sep 17 00:00:00 2001
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From: Bibo Mao <maobibo@loongson.cn>
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Date: Tue, 27 Aug 2024 11:58:07 +0800
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Subject: [PATCH 50/78] target/loongarch: Add compatible support about VM
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reboot
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With edk2-stable202408 LoongArch UEFI bios, CSR PGD register is set only
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if its value is equal to zero for boot cpu, it causes reboot issue. Since
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CSR PGD register is changed with linux kernel, UEFI BIOS cannot use it.
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Add workaround to clear CSR registers relative with TLB in function
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loongarch_cpu_reset_hold(), so that VM can reboot with edk2-stable202408
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UEFI bios.
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Signed-off-by: Bibo Mao <maobibo@loongson.cn>
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Reviewed-by: Song Gao <gaosong@loongson.cn>
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Message-Id: <20240827035807.3326293-1-maobibo@loongson.cn>
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Signed-off-by: Song Gao <gaosong@loongson.cn>
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Signed-off-by: Xianglai Li <lixianglai@loongson.cn>
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---
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target/loongarch/cpu.c | 14 ++++++++++++++
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1 file changed, 14 insertions(+)
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diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
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index d8a31929b4..2038984d02 100644
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--- a/target/loongarch/cpu.c
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+++ b/target/loongarch/cpu.c
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@@ -580,6 +580,20 @@ static void loongarch_cpu_reset_hold(Object *obj)
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env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0);
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env->CSR_MERRCTL = FIELD_DP64(env->CSR_MERRCTL, CSR_MERRCTL, ISMERR, 0);
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env->CSR_TID = cs->cpu_index;
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+ /*
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+ * Workaround for edk2-stable202408, CSR PGD register is set only if
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+ * its value is equal to zero for boot cpu, it causes reboot issue.
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+ *
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+ * Here clear CSR registers relative with TLB.
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+ */
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+ env->CSR_PGDH = 0;
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+ env->CSR_PGDL = 0;
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+ env->CSR_PWCL = 0;
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+ env->CSR_PWCH = 0;
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+ env->CSR_STLBPS = 0;
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+ env->CSR_EENTRY = 0;
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+ env->CSR_TLBRENTRY = 0;
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+ env->CSR_MERRENTRY = 0;
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for (n = 0; n < 4; n++) {
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env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV0, 0);
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--
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2.39.1
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