71 lines
2.8 KiB
Diff
71 lines
2.8 KiB
Diff
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From 8c61e09f435ff3a965867b0496f01682d679182f Mon Sep 17 00:00:00 2001
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From: Xiaoyao Li <xiaoyao.li@intel.com>
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Date: Wed, 14 Aug 2024 03:54:24 -0400
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Subject: [PATCH] target/i386: Enable fdp-excptn-only and zero-fcs-fds
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commit 7dddc3bb875e7141ab25931d0f30a1c319bc8457 upstream.
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- CPUID.(EAX=07H,ECX=0H):EBX[bit 6]: x87 FPU Data Pointer updated only
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on x87 exceptions if 1.
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- CPUID.(EAX=07H,ECX=0H):EBX[bit 13]: Deprecates FPU CS and FPU DS
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values if 1. i.e., X87 FCS and FDS are always zero.
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Define names for them so that they can be exposed to guest with -cpu host.
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Also define the bit field MACROs so that named cpu models can add it as
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well in the future.
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Intel-SIG: commit 7dddc3bb875e target/i386: Enable fdp-excptn-only and zero-fcs-fds
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Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
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Link: https://lore.kernel.org/r/20240814075431.339209-3-xiaoyao.li@intel.com
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Signed-off-by: Jason Zeng <jason.zeng@intel.com>
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---
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target/i386/cpu.c | 4 ++--
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target/i386/cpu.h | 4 ++++
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2 files changed, 6 insertions(+), 2 deletions(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index dfc0f7fd2d..d0aa2fb5ff 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -906,9 +906,9 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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.type = CPUID_FEATURE_WORD,
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.feat_names = {
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"fsgsbase", "tsc-adjust", "sgx", "bmi1",
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- "hle", "avx2", NULL, "smep",
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+ "hle", "avx2", "fdp-excptn-only", "smep",
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"bmi2", "erms", "invpcid", "rtm",
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- NULL, NULL, "mpx", NULL,
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+ NULL, "zero-fcs-fds", "mpx", NULL,
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"avx512f", "avx512dq", "rdseed", "adx",
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"smap", "avx512ifma", "pcommit", "clflushopt",
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"clwb", "intel-pt", "avx512pf", "avx512er",
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index b90182582f..b883e5e1d6 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -809,6 +809,8 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);
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#define CPUID_7_0_EBX_HLE (1U << 4)
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/* Intel Advanced Vector Extensions 2 */
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#define CPUID_7_0_EBX_AVX2 (1U << 5)
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+/* FPU data pointer updated only on x87 exceptions */
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+#define CPUID_7_0_EBX_FDP_EXCPTN_ONLY (1u << 6)
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/* Supervisor-mode Execution Prevention */
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#define CPUID_7_0_EBX_SMEP (1U << 7)
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/* 2nd Group of Advanced Bit Manipulation Extensions */
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@@ -819,6 +821,8 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);
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#define CPUID_7_0_EBX_INVPCID (1U << 10)
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/* Restricted Transactional Memory */
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#define CPUID_7_0_EBX_RTM (1U << 11)
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+/* Zero out FPU CS and FPU DS */
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+#define CPUID_7_0_EBX_ZERO_FCS_FDS (1U << 13)
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/* Memory Protection Extension */
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#define CPUID_7_0_EBX_MPX (1U << 14)
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/* AVX-512 Foundation */
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--
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2.41.0.windows.1
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