43 lines
1.5 KiB
Diff
43 lines
1.5 KiB
Diff
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From ad6ce039cab07b6a99ccaa36fbb0043ae85a74c9 Mon Sep 17 00:00:00 2001
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From: Peng Liang <liangpeng10@huawei.com>
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Date: Mon, 21 Sep 2020 22:14:20 +0800
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Subject: [PATCH] target/arm: clear EL2 and EL3 only when kvm is not enabled
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When has_el2 and has_el3 are disabled, which is the default value for
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virt machine, QEMU will clear the corresponding field in ID_PFR1_EL1 and
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ID_AA64PFR0_EL1 to not expose EL3 and EL2 to guest. Because KVM doesn't
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support to emulate ID registers in AArch64 before, it will not take
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effect. Hence, clear EL2 and EL3 only when kvm is not enabled for
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backwards compatibility.
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Signed-off-by: Peng Liang <liangpeng10@huawei.com>
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---
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target/arm/cpu.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/target/arm/cpu.c b/target/arm/cpu.c
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index 7ae2d3da56..3f62336acf 100644
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--- a/target/arm/cpu.c
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+++ b/target/arm/cpu.c
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@@ -1996,7 +1996,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
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}
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}
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- if (!cpu->has_el3) {
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+ if (!cpu->has_el3 && !kvm_enabled()) {
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/* If the has_el3 CPU property is disabled then we need to disable the
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* feature.
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*/
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@@ -2037,7 +2037,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
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cpu->pmceid1 = 0;
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}
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- if (!arm_feature(env, ARM_FEATURE_EL2)) {
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+ if (!arm_feature(env, ARM_FEATURE_EL2) && !kvm_enabled()) {
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/* Disable the hypervisor feature bits in the processor feature
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* registers if we don't have EL2. These are id_pfr1[15:12] and
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* id_aa64pfr0_el1[11:8].
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--
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2.23.0
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