44 lines
1.6 KiB
Diff
44 lines
1.6 KiB
Diff
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From 5489264cd9583855d45fd0c21f18387b649f6e44 Mon Sep 17 00:00:00 2001
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From: tangbinzy <tangbin_yewu@cmss.chinamobile.com>
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Date: Wed, 23 Nov 2022 15:26:59 +0300
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Subject: [PATCH 15/29] target/riscv/pmp: fix no pmp illegal intrs
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mainline inclusion
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commit 0fbb5d2d3c9ded9fbd3f6f993974cc5e88e28912
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category: bugfix
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-----------------------------------------------
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As per the privilege specification, any access from S/U mode should fail
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if no pmp region is configured and pmp is present, othwerwise access
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should succeed.
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Fixes: d102f19a208 (target/riscv/pmp: Raise exception if no PMP entry is configured)
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Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
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Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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Message-id: 20211214092659.15709-1-nikita.shubin@maquefel.me
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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Signed-off-by: tangbinzy <tangbin_yewu@cmss.chinamobile.com>
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---
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target/riscv/op_helper.c | 3 ++-
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1 file changed, 2 insertions(+), 1 deletion(-)
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diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
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index ee7c24efe7..58d992e98a 100644
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--- a/target/riscv/op_helper.c
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+++ b/target/riscv/op_helper.c
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@@ -146,7 +146,8 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
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uint64_t mstatus = env->mstatus;
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target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
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- if (!pmp_get_num_rules(env) && (prev_priv != PRV_M)) {
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+ if (riscv_feature(env, RISCV_FEATURE_PMP) &&
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+ !pmp_get_num_rules(env) && (prev_priv != PRV_M)) {
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riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
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}
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--
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2.27.0
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