39 lines
1.4 KiB
Diff
39 lines
1.4 KiB
Diff
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From 7f5cf2958ee5d178d058470031b96a82d3002a5c Mon Sep 17 00:00:00 2001
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From: qihao <qihao_yewu@cmss.chinamobile.com>
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Date: Wed, 1 Nov 2023 19:00:34 +0800
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Subject: [PATCH] hw/timer/npcm7xx_timer: Prevent timer from counting down past
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zero
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cheery-pick from 9ef2629712680e70cbf39d8b6cb1ec0e0e2e72fa
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The counter register is only 24-bits and counts down. If the timer is
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running but the qtimer to reset it hasn't fired off yet, there is a chance
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the regster read can return an invalid result.
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Signed-off-by: Chris Rauer <crauer@google.com>
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Message-id: 20230922181411.2697135-1-crauer@google.com
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: qihao_yewu <qihao_yewu@cmss.chinamobile.com>
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---
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hw/timer/npcm7xx_timer.c | 3 +++
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1 file changed, 3 insertions(+)
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diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c
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index 32f5e021f8..a8bd93aeb2 100644
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--- a/hw/timer/npcm7xx_timer.c
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+++ b/hw/timer/npcm7xx_timer.c
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@@ -138,6 +138,9 @@ static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, uint32_t count)
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/* Convert a time interval in nanoseconds to a timer cycle count. */
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static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns)
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{
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+ if (ns < 0) {
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+ return 0;
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+ }
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return clock_ns_to_ticks(t->ctrl->clock, ns) /
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npcm7xx_tcsr_prescaler(t->tcsr);
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}
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--
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2.27.0
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