40 lines
1.4 KiB
Diff
40 lines
1.4 KiB
Diff
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From 58a192d877acfe06964d91ef831597f833ac4f0c Mon Sep 17 00:00:00 2001
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From: xiaowanghe <xiaowanghe_yewu@cmss.chinamobile.com>
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Date: Mon, 14 Aug 2023 18:57:59 -0700
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Subject: [PATCH] hw/ssi: Fix Linux driver init issue with xilinx_spi
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cherry picked from commit a0eaa126af3c5a43937a22c58cfb9bb36e4a5001
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The problem is that the Linux driver expects the master transaction inhibit
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bit(R_SPICR_MTI) to be set during driver initialization so that it can
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detect the fifo size but QEMU defaults it to zero out of reset. The
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datasheet indicates this bit is active on reset.
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See page 25, SPI Control Register section:
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https://www.xilinx.com/content/dam/xilinx/support/documents/ip_documentation/axi_quad_spi/v3_2/pg153-axi-quad-spi.pdf
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Signed-off-by: Chris Rauer <crauer@google.com>
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Message-id: 20230323182811.2641044-1-crauer@google.com
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Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Wanghe Xiao <xiaowanghe_yewu@cmss.chinamobile.com>
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---
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hw/ssi/xilinx_spi.c | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c
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index b2819a7ff0..92e7cabf42 100644
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--- a/hw/ssi/xilinx_spi.c
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+++ b/hw/ssi/xilinx_spi.c
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@@ -156,6 +156,7 @@ static void xlx_spi_do_reset(XilinxSPI *s)
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txfifo_reset(s);
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s->regs[R_SPISSR] = ~0;
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+ s->regs[R_SPICR] = R_SPICR_MTI;
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xlx_spi_update_irq(s);
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xlx_spi_update_cs(s);
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}
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--
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2.41.0.windows.1
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