61 lines
2.2 KiB
Diff
61 lines
2.2 KiB
Diff
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From 8fe9899c39d86f9e0baf832744a7cfe19642a3fd Mon Sep 17 00:00:00 2001
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From: Jiaxi Chen <jiaxi.chen@linux.intel.com>
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Date: Fri, 3 Mar 2023 14:59:10 +0800
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Subject: [PATCH] target/i386: Add support for AVX-IFMA in CPUID enumeration
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commit a957a88416ecbec51e147cba9fe89b93f6646b3b upstream.
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AVX-IFMA is a new instruction in the latest Intel platform Sierra
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Forest. This instruction packed multiplies unsigned 52-bit integers and
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adds the low/high 52-bit products to Qword Accumulators.
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The bit definition:
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CPUID.(EAX=7,ECX=1):EAX[bit 23]
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Add CPUID definition for AVX-IFMA.
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Intel-SIG: commit a957a88416ec target/i386: Add support for AVX-IFMA in CPUID enumeration.
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Backport GNR and SRF ISA into QEMU-6.2
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Signed-off-by: Jiaxi Chen <jiaxi.chen@linux.intel.com>
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Signed-off-by: Tao Su <tao1.su@linux.intel.com>
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Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
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Message-Id: <20230303065913.1246327-4-tao1.su@linux.intel.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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[ Quanxian Wang: amend commit log ]
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Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
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---
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target/i386/cpu.c | 2 +-
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target/i386/cpu.h | 2 ++
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2 files changed, 3 insertions(+), 1 deletion(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index 3fc3b8041a..b19fb0cf87 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -876,7 +876,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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NULL, NULL, "fzrm", "fsrs",
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"fsrc", NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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- NULL, "amx-fp16", NULL, NULL,
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+ NULL, "amx-fp16", NULL, "avx-ifma",
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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},
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index c747e68a7a..2bcc127fac 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -893,6 +893,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
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#define CPUID_7_1_EAX_FSRC (1U << 12)
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/* Support Tile Computational Operations on FP16 Numbers */
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#define CPUID_7_1_EAX_AMX_FP16 (1U << 21)
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+/* Support for VPMADD52[H,L]UQ */
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+#define CPUID_7_1_EAX_AVX_IFMA (1U << 23)
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/* Do not exhibit MXCSR Configuration Dependent Timing (MCDT) behavior */
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#define CPUID_7_2_EDX_MCDT_NO (1U << 5)
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--
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2.27.0
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