38 lines
1.5 KiB
Diff
38 lines
1.5 KiB
Diff
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From 6872e7bf919dd5f2852c07850899cdb510eccfdf Mon Sep 17 00:00:00 2001
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From: xiaowanghe <xiaowanghe_yewu@cmss.chinamobile.com>
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Date: Tue, 1 Aug 2023 23:46:43 -0700
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Subject: [PATCH] disas/riscv Fix ctzw disassemble
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cherry picked from commit 270629024df1f9f4e704ce8325f958858c5cbff7
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Due to typo in opcode list, ctzw is disassembled as clzw instruction.
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Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>
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Fixes: 02c1b569a15b ("disas/riscv: Add Zb[abcs] instructions")
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Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
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Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
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Message-ID: <20230217151459.54649-1-ivan.klokov@syntacore.com>
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Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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Signed-off-by: Wanghe Xiao <xiaowanghe_yewu@cmss.chinamobile.com>
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---
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disas/riscv.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/disas/riscv.c b/disas/riscv.c
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index 793ad14c27..6768ec8188 100644
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--- a/disas/riscv.c
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+++ b/disas/riscv.c
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@@ -1189,7 +1189,7 @@ const rv_opcode_data opcode_data[] = {
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{ "max", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "maxu", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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- { "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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+ { "ctzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "slli.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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--
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2.41.0.windows.1
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