61 lines
2.4 KiB
Diff
61 lines
2.4 KiB
Diff
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From 5853333c9513caea541701c95a4ac691bb97452f Mon Sep 17 00:00:00 2001
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From: Xu Yandong <xuyandong2@huawei.com>
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Date: Tue, 19 Mar 2024 10:45:56 +0800
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Subject: [PATCH] cpu: add Cortex-A72 processor kvm target support
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The ARM Cortex-A72 is ARMv8-A micro-architecture,
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add kvm target to ARM Cortex-A72 processor definition.
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Signed-off-by: Xu Yandong <xuyandong2@huawei.com>
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Signed-off-by: Mingwang Li <limingwang@huawei.com>
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Signed-off-by: Yuan Zhang <zhangyuan162@huawei.com>
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---
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target/arm/cpu64.c | 2 +-
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target/arm/kvm-consts.h | 3 +++
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2 files changed, 4 insertions(+), 1 deletion(-)
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diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
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index 922eac3b61..471014b5a9 100644
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--- a/target/arm/cpu64.c
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+++ b/target/arm/cpu64.c
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@@ -710,6 +710,7 @@ static void aarch64_a72_initfn(Object *obj)
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ARMCPU *cpu = ARM_CPU(obj);
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cpu->dtb_compatible = "arm,cortex-a72";
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+ cpu->kvm_target = QEMU_KVM_ARM_TARGET_GENERIC_V8;
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set_feature(&cpu->env, ARM_FEATURE_V8);
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set_feature(&cpu->env, ARM_FEATURE_NEON);
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set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
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@@ -773,7 +774,6 @@ static void aarch64_kunpeng_920_initfn(Object *obj)
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cpu->isar.id_aa64dfr0 = 0x110305408;
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cpu->isar.id_aa64isar0 = 0x10211120;
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cpu->isar.id_aa64mmfr0 = 0x101125;
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- cpu->kvm_target = KVM_ARM_TARGET_GENERIC_V8;
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}
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static void aarch64_host_initfn(Object *obj)
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diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h
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index 7c6adc14f6..c034823170 100644
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--- a/target/arm/kvm-consts.h
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+++ b/target/arm/kvm-consts.h
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@@ -133,6 +133,8 @@ MISMATCH_CHECK(QEMU_PSCI_RET_DISABLED, PSCI_RET_DISABLED);
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#define QEMU_KVM_ARM_TARGET_CORTEX_A57 2
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#define QEMU_KVM_ARM_TARGET_XGENE_POTENZA 3
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#define QEMU_KVM_ARM_TARGET_CORTEX_A53 4
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+/* Generic ARM v8 target */
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+#define QEMU_KVM_ARM_TARGET_GENERIC_V8 5
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/* There's no kernel define for this: sentinel value which
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* matches no KVM target value for either 64 or 32 bit
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@@ -144,6 +146,7 @@ MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_FOUNDATION_V8, KVM_ARM_TARGET_FOUNDATION_V8);
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MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A57, KVM_ARM_TARGET_CORTEX_A57);
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MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_XGENE_POTENZA, KVM_ARM_TARGET_XGENE_POTENZA);
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MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A53, KVM_ARM_TARGET_CORTEX_A53);
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+MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_GENERIC_V8, KVM_ARM_TARGET_GENERIC_V8);
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#define CP_REG_ARM64 0x6000000000000000ULL
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#define CP_REG_ARM_COPROC_MASK 0x000000000FFF0000
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--
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2.27.0
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