40 lines
1.5 KiB
Diff
40 lines
1.5 KiB
Diff
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From 66eb68e54a521bc0dac015415a9eca25fe479543 Mon Sep 17 00:00:00 2001
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From: Zhenzhong Duan <zhenzhong.duan@intel.com>
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Date: Mon, 4 Nov 2024 20:55:34 +0800
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Subject: [PATCH] intel_iommu: Send IQE event when setting reserved bit in
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IQT_TAIL
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According to VTD spec, Figure 11-22, Invalidation Queue Tail Register,
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"When Descriptor Width (DW) field in Invalidation Queue Address Register
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(IQA_REG) is Set (256-bit descriptors), hardware treats bit-4 as reserved
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and a value of 1 in the bit will result in invalidation queue error."
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Current code missed to send IQE event to guest, fix it.
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Fixes: c0c1d351849b ("intel_iommu: add 256 bits qi_desc support")
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Suggested-by: Yi Liu <yi.l.liu@intel.com>
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Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
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Message-Id: <20241104125536.1236118-2-zhenzhong.duan@intel.com>
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Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
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Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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Signed-off-by: Zhongrui Tang <tangzhongrui_yewu@cmss.chinamobile.com>
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---
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hw/i386/intel_iommu.c | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
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index 5085a6fee3..3da56e439e 100644
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--- a/hw/i386/intel_iommu.c
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+++ b/hw/i386/intel_iommu.c
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@@ -2813,6 +2813,7 @@ static void vtd_handle_iqt_write(IntelIOMMUState *s)
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if (s->iq_dw && (val & VTD_IQT_QT_256_RSV_BIT)) {
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error_report_once("%s: RSV bit is set: val=0x%"PRIx64,
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__func__, val);
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+ vtd_handle_inv_queue_error(s);
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return;
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}
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s->iq_tail = VTD_IQT_QT(s->iq_dw, val);
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--
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2.41.0.windows.1
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