99 lines
3.5 KiB
Diff
99 lines
3.5 KiB
Diff
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From 98ca0862f34c891a0e381bd382306398b88ac5bc Mon Sep 17 00:00:00 2001
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From: Kunkun Jiang <jiangkunkun@huawei.com>
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Date: Fri, 18 Nov 2022 15:22:56 +0800
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Subject: [PATCH 33/36] Revert "hw/arm/smmuv3: Improve stage1 ASID
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invalidation"
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This reverts commit de53feaa37a267a21ed30a642e1e64c5fcfbc4a4.
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Signed-off-by: Kunkun Jiang <jiangkunkun@huawei.com>
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---
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hw/arm/smmuv3.c | 44 ++------------------------------------------
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hw/arm/trace-events | 1 -
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2 files changed, 2 insertions(+), 43 deletions(-)
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diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
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index f4de66827d..0e8fe646aa 100644
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--- a/hw/arm/smmuv3.c
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+++ b/hw/arm/smmuv3.c
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@@ -840,31 +840,6 @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr,
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memory_region_notify_iommu_one(n, &event);
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}
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-/**
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- * smmuv3_notify_asid - call the notifier @n for a given asid
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- *
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- * @mr: IOMMU mr region handle
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- * @n: notifier to be called
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- * @asid: address space ID or negative value if we don't care
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- */
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-static void smmuv3_notify_asid(IOMMUMemoryRegion *mr,
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- IOMMUNotifier *n, int asid)
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-{
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- IOMMUTLBEvent event = {};
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-
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- event.type = IOMMU_NOTIFIER_UNMAP;
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- event.entry.target_as = &address_space_memory;
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- event.entry.perm = IOMMU_NONE;
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- event.entry.granularity = IOMMU_INV_GRAN_PASID;
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- event.entry.flags = IOMMU_INV_FLAGS_ARCHID;
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- event.entry.arch_id = asid;
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- event.entry.iova = n->start;
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- event.entry.addr_mask = n->end - n->start;
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-
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- memory_region_notify_iommu_one(n, &event);
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-}
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-
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-
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/* invalidate an asid/iova range tuple in all mr's */
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static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, dma_addr_t iova,
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uint8_t tg, uint64_t num_pages)
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@@ -942,22 +917,6 @@ smmuv3_invalidate_ste(gpointer key, gpointer value, gpointer user_data)
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return true;
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}
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-static void smmuv3_s1_asid_inval(SMMUState *s, uint16_t asid)
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-{
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- SMMUDevice *sdev;
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-
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- trace_smmuv3_s1_asid_inval(asid);
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- QLIST_FOREACH(sdev, &s->devices_with_notifiers, next) {
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- IOMMUMemoryRegion *mr = &sdev->iommu;
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- IOMMUNotifier *n;
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-
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- IOMMU_NOTIFIER_FOREACH(n, mr) {
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- smmuv3_notify_asid(mr, n, asid);
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- }
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- }
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- smmu_iotlb_inv_asid(s, asid);
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-}
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-
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static int smmuv3_cmdq_consume(SMMUv3State *s)
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{
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SMMUState *bs = ARM_SMMU(s);
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@@ -1072,7 +1031,8 @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
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uint16_t asid = CMD_ASID(&cmd);
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trace_smmuv3_cmdq_tlbi_nh_asid(asid);
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- smmuv3_s1_asid_inval(bs, asid);
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+ smmu_inv_notifiers_all(&s->smmu_state);
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+ smmu_iotlb_inv_asid(bs, asid);
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break;
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}
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case SMMU_CMD_TLBI_NH_ALL:
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diff --git a/hw/arm/trace-events b/hw/arm/trace-events
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index 1447ad5a90..2dee296c8f 100644
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--- a/hw/arm/trace-events
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+++ b/hw/arm/trace-events
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@@ -46,7 +46,6 @@ smmuv3_cmdq_cfgi_cd(uint32_t sid) "sid=0x%x"
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smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache HIT for sid=0x%x (hits=%d, misses=%d, hit rate=%d)"
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smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache MISS for sid=0x%x (hits=%d, misses=%d, hit rate=%d)"
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smmuv3_s1_range_inval(int vmid, int asid, uint64_t addr, uint8_t tg, uint64_t num_pages, uint8_t ttl, bool leaf) "vmid=%d asid=%d addr=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64" ttl=%d leaf=%d"
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-smmuv3_s1_asid_inval(int asid) "asid=%d"
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smmuv3_cmdq_tlbi_nh(void) ""
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smmuv3_cmdq_tlbi_nh_asid(uint16_t asid) "asid=%d"
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smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid=0x%x"
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--
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2.27.0
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