33 lines
1.1 KiB
Diff
33 lines
1.1 KiB
Diff
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From 3371917ea92265377f87692a717397267416c4aa Mon Sep 17 00:00:00 2001
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From: Peng Liang <liangpeng10@huawei.com>
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Date: Wed, 16 Sep 2020 19:40:28 +0800
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Subject: [PATCH] target/arm: only set ID_PFR1_EL1.GIC for AArch32 guest
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Some AArch64 CPU doesn't support AArch32 mode, and the values of AArch32
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registers are all 0. Hence, We'd better not to modify AArch32 registers
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in AArch64 mode.
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Signed-off-by: zhanghailiang <zhang.zhanghailiang@huawei.com>
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Signed-off-by: Peng Liang <liangpeng10@huawei.com>
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Signed-off-by: Dongxu Sun <sundongxu3@huawei.com>
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---
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target/arm/helper.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/target/arm/helper.c b/target/arm/helper.c
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index 79f77705c3..4c7b4cadfa 100644
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--- a/target/arm/helper.c
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+++ b/target/arm/helper.c
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@@ -6718,7 +6718,7 @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
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ARMCPU *cpu = env_archcpu(env);
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uint64_t pfr1 = cpu->isar.regs[ID_PFR1];
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- if (env->gicv3state) {
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+ if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && env->gicv3state) {
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pfr1 |= 1 << 28;
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}
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return pfr1;
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--
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2.27.0
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