43 lines
1.4 KiB
Diff
43 lines
1.4 KiB
Diff
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From 696abba190a0daad488d709d733f0d1f10df6f89 Mon Sep 17 00:00:00 2001
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From: Ying Fang <fangying1@huawei.com>
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Date: Mon, 29 Jul 2019 16:16:35 +0800
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Subject: [PATCH 1/6] pl011: reset read FIFO when UARTTIMSC=0 & UARTICR=0xffff
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We can enable ACPI when AArch64 Linux is booted with QEMU and UEFI (AAVMF).
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When VM is booting and the SBSA driver has not initialized, writting data
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that exceds 32 bytes will cause the read FIFO full and proceeding data will
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be lost. The searil port appears to be stuck in this abnormal situation.
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A hack to reset read FIFO when UARTTIMSC=0 & UARTICR=0xffff appears to
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resolve the issue.
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The question is fully discussed at
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https://www.spinics.net/lists/linux-serial/msg23163.html
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Signed-off-by: Haibin Wang <wanghaibin.wang@huawei.com>
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Reviewed-by: Shannon Zhao <shannon.zhaosl@gmail.com>
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Reviewed-by: Ying Fang <fangying1@huawei.com>
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Signed-off-by: Yan Wang <wangyan122@huawei.com>
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---
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hw/char/pl011.c | 4 ++++
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1 file changed, 4 insertions(+)
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diff --git a/hw/char/pl011.c b/hw/char/pl011.c
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index 6e2d7f7..8ca2a4e 100644
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--- a/hw/char/pl011.c
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+++ b/hw/char/pl011.c
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@@ -255,6 +255,10 @@ static void pl011_write(void *opaque, hwaddr offset,
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case 17: /* UARTICR */
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s->int_level &= ~value;
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pl011_update(s);
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+ if (!s->int_enabled && !s->int_level) {
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+ s->read_count = 0;
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+ s->read_pos = 0;
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+ }
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break;
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case 18: /* UARTDMACR */
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s->dmacr = value;
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--
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1.9.1
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