43 lines
1.8 KiB
Diff
43 lines
1.8 KiB
Diff
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From 45e80d1d71f7f4b50b47ec61560a77edd80badc1 Mon Sep 17 00:00:00 2001
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From: gubin <gubin_yewu@cmss.chinamobile.com>
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Date: Thu, 2 Jan 2025 10:35:05 +0800
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Subject: [PATCH] target/arm: take HSTR traps of cp15 accesses to EL2, not EL1
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cherry-pick from fbe5ac5671a9cfcc7f4aee9a5fac7720eea08876
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The HSTR_EL2 register allows the hypervisor to trap AArch32 EL1 and
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EL0 accesses to cp15 registers. We incorrectly implemented this so
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they trap to EL1 when we detect the need for a HSTR trap at code
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generation time. (The check in access_check_cp_reg() which we do at
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runtime to catch traps from EL0 is correctly routing them to EL2.)
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Use the correct target EL when generating the code to take the trap.
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Cc: qemu-stable@nongnu.org
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Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2226
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Fixes: 049edada5e93df ("target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1")
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20240325133116.2075362-1-peter.maydell@linaro.org
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Signed-off-by: gubin <gubin_yewu@cmss.chinamobile.com>
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---
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target/arm/tcg/translate.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
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index b3660173d1..e555e885a1 100644
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--- a/target/arm/tcg/translate.c
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+++ b/target/arm/tcg/translate.c
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@@ -4584,7 +4584,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
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tcg_gen_andi_i32(t, t, 1u << maskbit);
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tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, over.label);
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- gen_exception_insn(s, 0, EXCP_UDEF, syndrome);
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+ gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2);
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/*
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* gen_exception_insn() will set is_jmp to DISAS_NORETURN,
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* but since we're conditionally branching over it, we want
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--
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2.41.0.windows.1
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