44 lines
1.3 KiB
Diff
44 lines
1.3 KiB
Diff
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From 7d4bc795419a69457ee5f2e32674183dc009d48f Mon Sep 17 00:00:00 2001
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From: Yanjing Zhou <zhouyanjing@hygon.cn>
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Date: Wed, 15 May 2024 13:49:19 +0800
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Subject: [PATCH] target/i386: Add Hygon Dhyana-v3 CPU model
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Add the following feature bits for Dhyana CPU model:
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perfctr-core, clzero, xsaveerptr, aes, pclmulqdq, sha-ni
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Disable xsaves feature bit for Erratum 1386
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Signed-off-by: Yanjing Zhou <zhouyanjing@hygon.cn>
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---
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target/i386/cpu.c | 14 ++++++++++++++
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1 file changed, 14 insertions(+)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index fd32c64f99..f4c22f32c6 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -4793,6 +4793,20 @@ static const X86CPUDefinition builtin_x86_defs[] = {
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{ /* end of list */ }
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},
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},
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+ { .version = 3,
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+ .props = (PropValue[]) {
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+ { "xsaves", "off" },
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+ { "perfctr-core", "on" },
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+ { "clzero", "on" },
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+ { "xsaveerptr", "on" },
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+ { "aes", "on" },
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+ { "pclmulqdq", "on" },
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+ { "sha-ni", "on" },
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+ { "model-id",
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+ "Hygon Dhyana-v3 processor" },
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+ { /* end of list */ }
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+ },
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+ },
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{ /* end of list */ }
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}
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},
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--
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2.41.0.windows.1
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