40 lines
1.5 KiB
Diff
40 lines
1.5 KiB
Diff
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From 1ad09007da426e9cd1585babcdd4de25ddfb2f8b Mon Sep 17 00:00:00 2001
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From: gubin <gubin_yewu@cmss.chinamobile.com>
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Date: Thu, 28 Nov 2024 14:39:05 +0800
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Subject: [PATCH] target/arm: Fix incorrect aa64_tidcp1 feature check
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cherry-pick from ee0a2e3c9d2991a11c13ffadb15e4d0add43c257
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A typo in the implementation of isar_feature_aa64_tidcp1() means we
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were checking the field in the wrong ID register, so we might have
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provided the feature on CPUs that don't have it and not provided
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it on CPUs that should have it. Correct this bug.
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Cc: qemu-stable@nongnu.org
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Fixes: 9cd0c0dec97be9 "target/arm: Implement FEAT_TIDCP1"
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Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2120
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20240123160333.958841-1-peter.maydell@linaro.org
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Signed-off-by: gubin <gubin_yewu@cmss.chinamobile.com>
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---
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target/arm/cpu-features.h | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
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index 954d358268..165a497f7b 100644
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--- a/target/arm/cpu-features.h
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+++ b/target/arm/cpu-features.h
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@@ -771,7 +771,7 @@ static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id)
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static inline bool isar_feature_aa64_tidcp1(const ARMISARegisters *id)
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{
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- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR1, TIDCP1) != 0;
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+ return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, TIDCP1) != 0;
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}
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static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id)
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--
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2.41.0.windows.1
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