62 lines
2.2 KiB
Diff
62 lines
2.2 KiB
Diff
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From 25d08629eab566f5a47bf915a86e20318ee1cf08 Mon Sep 17 00:00:00 2001
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From: Jiaxi Chen <jiaxi.chen@linux.intel.com>
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Date: Fri, 3 Mar 2023 14:59:08 +0800
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Subject: [PATCH] target/i386: Add support for CMPCCXADD in CPUID enumeration
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commit a9ce107fd0f2017af84255a9cf6542fa3eb3e214 upstream.
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CMPccXADD is a new set of instructions in the latest Intel platform
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Sierra Forest. This new instruction set includes a semaphore operation
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that can compare and add the operands if condition is met, which can
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improve database performance.
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The bit definition:
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CPUID.(EAX=7,ECX=1):EAX[bit 7]
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Add CPUID definition for CMPCCXADD.
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Intel-SIG: commit a9ce107fd0f2 target/i386: Add support for CMPCCXADD in CPUID enumeration.
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Backport GNR and SRF ISA into QEMU-6.2
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Signed-off-by: Jiaxi Chen <jiaxi.chen@linux.intel.com>
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Signed-off-by: Tao Su <tao1.su@linux.intel.com>
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Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
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Message-Id: <20230303065913.1246327-2-tao1.su@linux.intel.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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[ Quanxian Wang: amend commit log ]
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Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
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---
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target/i386/cpu.c | 2 +-
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target/i386/cpu.h | 2 ++
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2 files changed, 3 insertions(+), 1 deletion(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index 58124071da..47c2d9da80 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -872,7 +872,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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.type = CPUID_FEATURE_WORD,
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.feat_names = {
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NULL, NULL, NULL, NULL,
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- "avx-vnni", "avx512-bf16", NULL, NULL,
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+ "avx-vnni", "avx512-bf16", NULL, "cmpccxadd",
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NULL, NULL, "fzrm", "fsrs",
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"fsrc", NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index 37c687d4d8..4a7362ee07 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -883,6 +883,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
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#define CPUID_7_1_EAX_AVX_VNNI (1U << 4)
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/* AVX512 BFloat16 Instruction */
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#define CPUID_7_1_EAX_AVX512_BF16 (1U << 5)
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+/* CMPCCXADD Instructions */
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+#define CPUID_7_1_EAX_CMPCCXADD (1U << 7)
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/* Fast Zero REP MOVS */
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#define CPUID_7_1_EAX_FZRM (1U << 10)
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/* Fast Short REP STOS */
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--
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2.27.0
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