58 lines
2.1 KiB
Diff
58 lines
2.1 KiB
Diff
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From 69eedbfc873ded9bf35439b813e9f6a7431dc727 Mon Sep 17 00:00:00 2001
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From: Richard Henderson <richard.henderson@linaro.org>
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Date: Sat, 8 Feb 2020 12:58:12 +0000
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Subject: [PATCH 09/13] target/arm: Enable ARMv8.2-ATS1E1 in -cpu max
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This includes enablement of ARMv8.1-PAN.
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Message-id: 20200208125816.14954-17-richard.henderson@linaro.org
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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---
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target/arm/cpu.c | 4 ++++
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target/arm/cpu64.c | 5 +++++
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2 files changed, 9 insertions(+)
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diff --git a/target/arm/cpu.c b/target/arm/cpu.c
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index a23c71db..119bd275 100644
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--- a/target/arm/cpu.c
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+++ b/target/arm/cpu.c
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@@ -2484,6 +2484,10 @@ static void arm_max_initfn(Object *obj)
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t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
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cpu->isar.mvfr2 = t;
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+ t = cpu->id_mmfr3;
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+ t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
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+ cpu->id_mmfr3 = t;
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+
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t = cpu->id_mmfr4;
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t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
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cpu->id_mmfr4 = t;
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diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
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index 7ad8b5e2..a0d07fd7 100644
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--- a/target/arm/cpu64.c
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+++ b/target/arm/cpu64.c
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@@ -362,6 +362,7 @@ static void aarch64_max_initfn(Object *obj)
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t = cpu->isar.id_aa64mmfr1;
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t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
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t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
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+ t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */
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cpu->isar.id_aa64mmfr1 = t;
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/* Replicate the same data to the 32-bit id registers. */
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@@ -382,6 +383,10 @@ static void aarch64_max_initfn(Object *obj)
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u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
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cpu->isar.id_isar6 = u;
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+ u = cpu->id_mmfr3;
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+ u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
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+ cpu->id_mmfr3 = u;
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+
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/*
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* FIXME: We do not yet support ARMv8.2-fp16 for AArch32 yet,
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* so do not set MVFR1.FPHP. Strictly speaking this is not legal,
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--
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2.25.1
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