39 lines
1.3 KiB
Diff
39 lines
1.3 KiB
Diff
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From fac9784bbedb50dc964feb9cf70b6f37472fcf60 Mon Sep 17 00:00:00 2001
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From: Nicolin Chen <nicolinc@nvidia.com>
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Date: Fri, 21 Apr 2023 22:10:44 -0700
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Subject: [PATCH] hw/arm/smmuv3: Check idr registers for STE_S1CDMAX and
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STE_S1STALLD
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With nested translation, the underlying HW could support those two fields.
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Allow them according to the updated idr registers after the hw_info ioctl.
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Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
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---
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hw/arm/smmuv3.c | 5 +++--
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1 file changed, 3 insertions(+), 2 deletions(-)
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diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
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index 4208325ab3..253d297eec 100644
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--- a/hw/arm/smmuv3.c
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+++ b/hw/arm/smmuv3.c
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@@ -622,13 +622,14 @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg,
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}
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}
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- if (STE_S1CDMAX(ste) != 0) {
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+ if (!FIELD_EX32(s->idr[1], IDR1, SSIDSIZE) && STE_S1CDMAX(ste) != 0) {
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qemu_log_mask(LOG_UNIMP,
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"SMMUv3 does not support multiple context descriptors yet\n");
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goto bad_ste;
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}
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- if (STE_S1STALLD(ste)) {
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+ /* STALL_MODEL being 0b01 means "stall is not supported" */
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+ if ((FIELD_EX32(s->idr[0], IDR0, STALL_MODEL) & 0x1) && STE_S1STALLD(ste)) {
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qemu_log_mask(LOG_UNIMP,
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"SMMUv3 S1 stalling fault model not allowed yet\n");
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goto bad_ste;
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--
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2.41.0.windows.1
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