63 lines
2.3 KiB
Diff
63 lines
2.3 KiB
Diff
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From 165d587b52f7c8459d9a9deca389610f9165b33a Mon Sep 17 00:00:00 2001
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From: Quanxian Wang <quanxian.wang@intel.com>
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Date: Wed, 8 Nov 2023 12:44:56 +0800
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Subject: [PATCH] target/i386: Add support for AVX-NE-CONVERT in CPUID
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enumeration
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commit ecd2e6ca037d7bf3673c5478590d686d5cd6135a upstream.
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AVX-NE-CONVERT is a new set of instructions which can convert low
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precision floating point like BF16/FP16 to high precision floating point
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FP32, as well as convert FP32 elements to BF16. This instruction allows
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the platform to have improved AI capabilities and better compatibility.
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The bit definition:
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CPUID.(EAX=7,ECX=1):EDX[bit 5]
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Add CPUID definition for AVX-NE-CONVERT.
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Intel-SIG: commit ecd2e6ca037d target/i386: Add support for AVX-NE-CONVERT in CPUID enumeration.
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Backport GNR and SRF ISA into QEMU-6.2
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Signed-off-by: Jiaxi Chen <jiaxi.chen@linux.intel.com>
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Signed-off-by: Tao Su <tao1.su@linux.intel.com>
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Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
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Message-Id: <20230303065913.1246327-6-tao1.su@linux.intel.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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[ Quanxian Wang: amend commit log ]
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Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
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---
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target/i386/cpu.c | 2 +-
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target/i386/cpu.h | 2 ++
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2 files changed, 3 insertions(+), 1 deletion(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index a14284a81b..d36174d689 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -911,7 +911,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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.type = CPUID_FEATURE_WORD,
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.feat_names = {
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NULL, NULL, NULL, NULL,
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- "avx-vnni-int8", NULL, NULL, NULL,
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+ "avx-vnni-int8", "avx-ne-convert", NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index b81d77084c..93c8bd6a13 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -898,6 +898,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
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#define CPUID_7_1_EAX_AVX_IFMA (1U << 23)
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/* Support for VPDPB[SU,UU,SS]D[,S] */
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#define CPUID_7_1_EDX_AVX_VNNI_INT8 (1U << 4)
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+/* AVX NE CONVERT Instructions */
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+#define CPUID_7_1_EDX_AVX_NE_CONVERT (1U << 5)
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/* Do not exhibit MXCSR Configuration Dependent Timing (MCDT) behavior */
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#define CPUID_7_2_EDX_MCDT_NO (1U << 5)
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--
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2.27.0
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