63 lines
2.3 KiB
Diff
63 lines
2.3 KiB
Diff
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From c362956eb88558991bee59e43d7db52c8bc7e5f5 Mon Sep 17 00:00:00 2001
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From: Jiaxi Chen <jiaxi.chen@linux.intel.com>
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Date: Fri, 3 Mar 2023 14:59:09 +0800
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Subject: [PATCH] target/i386: Add support for AMX-FP16 in CPUID enumeration
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commit 99ed8445ea27742a4df40f51a3a5fbd6f8e76fa5 upstream.
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Latest Intel platform Granite Rapids has introduced a new instruction -
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AMX-FP16, which performs dot-products of two FP16 tiles and accumulates
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the results into a packed single precision tile. AMX-FP16 adds FP16
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capability and allows a FP16 GPU trained model to run faster without
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loss of accuracy or added SW overhead.
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The bit definition:
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CPUID.(EAX=7,ECX=1):EAX[bit 21]
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Add CPUID definition for AMX-FP16.
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Intel-SIG: commit 99ed8445ea27 target/i386: Add support for AMX-FP16 in CPUID enumeration.
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Backport GNR and SRF ISA into QEMU-6.2
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Signed-off-by: Jiaxi Chen <jiaxi.chen@linux.intel.com>
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Signed-off-by: Tao Su <tao1.su@linux.intel.com>
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Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
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Message-Id: <20230303065913.1246327-3-tao1.su@linux.intel.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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[ Quanxian Wang: amend commit log ]
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Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
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---
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target/i386/cpu.c | 2 +-
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target/i386/cpu.h | 2 ++
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2 files changed, 3 insertions(+), 1 deletion(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index 47c2d9da80..3fc3b8041a 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -876,7 +876,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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NULL, NULL, "fzrm", "fsrs",
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"fsrc", NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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- NULL, NULL, NULL, NULL,
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+ NULL, "amx-fp16", NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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},
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index 4a7362ee07..c747e68a7a 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -891,6 +891,8 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
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#define CPUID_7_1_EAX_FSRS (1U << 11)
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/* Fast Short REP CMPS/SCAS */
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#define CPUID_7_1_EAX_FSRC (1U << 12)
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+/* Support Tile Computational Operations on FP16 Numbers */
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+#define CPUID_7_1_EAX_AMX_FP16 (1U << 21)
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/* Do not exhibit MXCSR Configuration Dependent Timing (MCDT) behavior */
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#define CPUID_7_2_EDX_MCDT_NO (1U << 5)
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--
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2.27.0
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