56 lines
2.3 KiB
Diff
56 lines
2.3 KiB
Diff
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From f677a8f2311e823a87ec70dbdbc07712d54e5a85 Mon Sep 17 00:00:00 2001
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From: Song Gao <gaosong@loongson.cn>
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Date: Fri, 5 Jul 2024 10:18:38 +0800
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Subject: [PATCH 48/78] target/loongarch: Set CSR_PRCFG1 and CSR_PRCFG2 values
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We set the value of register CSR_PRCFG3, but left out CSR_PRCFG1
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and CSR_PRCFG2. Set CSR_PRCFG1 and CSR_PRCFG2 according to the
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default values of the physical machine.
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Signed-off-by: Song Gao <gaosong@loongson.cn>
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Reviewed-by: Bibo Mao <maobibo@loongson.cn>
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Message-Id: <20240705021839.1004374-1-gaosong@loongson.cn>
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Signed-off-by: Xianglai Li <lixianglai@loongson.cn>
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---
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target/loongarch/cpu.c | 17 ++++++++++++-----
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1 file changed, 12 insertions(+), 5 deletions(-)
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diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
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index f89740a5aa..5bb9e5656a 100644
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--- a/target/loongarch/cpu.c
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+++ b/target/loongarch/cpu.c
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@@ -472,6 +472,18 @@ static void loongarch_la464_initfn(Object *obj)
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env->cpucfg[20] = data;
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env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa);
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+
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+ env->CSR_PRCFG1 = FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, SAVE_NUM, 8);
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+ env->CSR_PRCFG1 = FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, TIMER_BITS, 0x2f);
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+ env->CSR_PRCFG1 = FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, VSMAX, 7);
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+
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+ env->CSR_PRCFG2 = 0x3ffff000;
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+
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+ env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, TLB_TYPE, 2);
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+ env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, MTLB_ENTRY, 63);
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+ env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS, 7);
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+ env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS, 8);
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+
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loongarch_cpu_post_init(obj);
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}
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@@ -569,11 +581,6 @@ static void loongarch_cpu_reset_hold(Object *obj)
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env->CSR_MERRCTL = FIELD_DP64(env->CSR_MERRCTL, CSR_MERRCTL, ISMERR, 0);
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env->CSR_TID = cs->cpu_index;
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- env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, TLB_TYPE, 2);
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- env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, MTLB_ENTRY, 63);
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- env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS, 7);
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- env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS, 8);
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-
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for (n = 0; n < 4; n++) {
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env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV0, 0);
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env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV1, 0);
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--
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2.39.1
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