34 lines
1.3 KiB
Diff
34 lines
1.3 KiB
Diff
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From 8a43c9379651fbf9d015240d6dc7c4b90ce98683 Mon Sep 17 00:00:00 2001
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From: Bibo Mao <maobibo@loongson.cn>
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Date: Wed, 6 Dec 2023 16:18:39 +0800
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Subject: [PATCH] target/loongarch: Add timer information dump support
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Timer emulation sometimes is problematic especially when vm is running in
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kvm mode. This patch adds registers dump support relative with timer
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hardware, so that it is easier to find the problems.
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Signed-off-by: Bibo Mao <maobibo@loongson.cn>
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Reviewed-by: Song Gao <gaosong@loongson.cn>
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Message-Id: <20231206081839.2290178-1-maobibo@loongson.cn>
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Signed-off-by: Song Gao <gaosong@loongson.cn>
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---
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target/loongarch/cpu.c | 2 ++
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1 file changed, 2 insertions(+)
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diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
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index fc075952e6..db9a421cc4 100644
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--- a/target/loongarch/cpu.c
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+++ b/target/loongarch/cpu.c
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@@ -762,6 +762,8 @@ void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
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qemu_fprintf(f, "TLBRENTRY=%016" PRIx64 "\n", env->CSR_TLBRENTRY);
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qemu_fprintf(f, "TLBRBADV=%016" PRIx64 "\n", env->CSR_TLBRBADV);
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qemu_fprintf(f, "TLBRERA=%016" PRIx64 "\n", env->CSR_TLBRERA);
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+ qemu_fprintf(f, "TCFG=%016" PRIx64 "\n", env->CSR_TCFG);
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+ qemu_fprintf(f, "TVAL=%016" PRIx64 "\n", env->CSR_TVAL);
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/* fpr */
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if (flags & CPU_DUMP_FPU) {
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--
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2.27.0
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