109 lines
4.5 KiB
Diff
109 lines
4.5 KiB
Diff
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From 110184b14d17c13e046e9c4ebed6c3cec29b31d0 Mon Sep 17 00:00:00 2001
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From: Xin Li <xin3.li@intel.com>
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Date: Wed, 8 Nov 2023 23:20:07 -0800
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Subject: [PATCH] target/i386: add support for FRED in CPUID enumeration
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commit c1acad9f72d14daf918563eb77d2b31c39fbd06a upstream.
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FRED, i.e., the Intel flexible return and event delivery architecture,
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defines simple new transitions that change privilege level (ring
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transitions).
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The new transitions defined by the FRED architecture are FRED event
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delivery and, for returning from events, two FRED return instructions.
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FRED event delivery can effect a transition from ring 3 to ring 0, but
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it is used also to deliver events incident to ring 0. One FRED
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instruction (ERETU) effects a return from ring 0 to ring 3, while the
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other (ERETS) returns while remaining in ring 0. Collectively, FRED
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event delivery and the FRED return instructions are FRED transitions.
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In addition to these transitions, the FRED architecture defines a new
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instruction (LKGS) for managing the state of the GS segment register.
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The LKGS instruction can be used by 64-bit operating systems that do
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not use the new FRED transitions.
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WRMSRNS is an instruction that behaves exactly like WRMSR, with the
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only difference being that it is not a serializing instruction by
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default. Under certain conditions, WRMSRNS may replace WRMSR to improve
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performance. FRED uses it to switch RSP0 in a faster manner.
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Search for the latest FRED spec in most search engines with this search
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pattern:
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site:intel.com FRED (flexible return and event delivery) specification
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The CPUID feature flag CPUID.(EAX=7,ECX=1):EAX[17] enumerates FRED, and
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the CPUID feature flag CPUID.(EAX=7,ECX=1):EAX[18] enumerates LKGS, and
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the CPUID feature flag CPUID.(EAX=7,ECX=1):EAX[19] enumerates WRMSRNS.
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Add CPUID definitions for FRED/LKGS/WRMSRNS, and expose them to KVM guests.
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Because FRED relies on LKGS and WRMSRNS, add that to feature dependency
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map.
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Intel-SIG: commit c1acad9f72d1 target/i386: add support for FRED in CPUID enumeration
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Tested-by: Shan Kang <shan.kang@intel.com>
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Signed-off-by: Xin Li <xin3.li@intel.com>
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Message-ID: <20231109072012.8078-2-xin3.li@intel.com>
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[Fix order of dependencies, add dependencies from LM to FRED. - Paolo]
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Signed-off-by: Jason Zeng <jason.zeng@intel.com>
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---
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target/i386/cpu.c | 14 +++++++++++++-
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target/i386/cpu.h | 6 ++++++
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2 files changed, 19 insertions(+), 1 deletion(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index 860934b39f..47f00392be 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -966,7 +966,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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"avx-vnni", "avx512-bf16", NULL, "cmpccxadd",
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NULL, NULL, "fzrm", "fsrs",
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"fsrc", NULL, NULL, NULL,
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- NULL, NULL, NULL, NULL,
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+ NULL, "fred", "lkgs", "wrmsrns",
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NULL, "amx-fp16", NULL, "avx-ifma",
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NULL, NULL, "lam", NULL,
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NULL, NULL, NULL, NULL,
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@@ -1553,6 +1553,18 @@ static FeatureDep feature_dependencies[] = {
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.from = { FEAT_7_0_ECX, CPUID_7_0_ECX_WAITPKG },
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.to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE },
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},
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+ {
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+ .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM },
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+ .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED },
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+ },
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+ {
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+ .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_LKGS },
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+ .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED },
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+ },
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+ {
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+ .from = { FEAT_7_1_EAX, CPUID_7_1_EAX_WRMSRNS },
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+ .to = { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED },
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+ },
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};
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typedef struct X86RegisterInfo32 {
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index 21fb769cce..f392626f98 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -941,6 +941,12 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
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#define CPUID_7_1_EDX_AMX_COMPLEX (1U << 8)
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/* PREFETCHIT0/1 Instructions */
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#define CPUID_7_1_EDX_PREFETCHITI (1U << 14)
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+/* Flexible return and event delivery (FRED) */
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+#define CPUID_7_1_EAX_FRED (1U << 17)
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+/* Load into IA32_KERNEL_GS_BASE (LKGS) */
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+#define CPUID_7_1_EAX_LKGS (1U << 18)
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+/* Non-Serializing Write to Model Specific Register (WRMSRNS) */
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+#define CPUID_7_1_EAX_WRMSRNS (1U << 19)
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/* Do not exhibit MXCSR Configuration Dependent Timing (MCDT) behavior */
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#define CPUID_7_2_EDX_MCDT_NO (1U << 5)
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--
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2.41.0.windows.1
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