41 lines
1.4 KiB
Diff
41 lines
1.4 KiB
Diff
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From 87871b854241cc52f967805e005bdd66a923c555 Mon Sep 17 00:00:00 2001
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From: Paolo Bonzini <pbonzini@redhat.com>
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Date: Wed, 3 Jul 2024 13:42:49 +0200
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Subject: [PATCH] target/i386: add sha512, sm3, sm4 feature bits
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commit 78be258c0eeba3d5613c37888889e84f2ba9bd94 upstream.
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SHA512, SM3, SM4 (CPUID[EAX=7,ECX=1).EAX bits 0 to 2) is supported by
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Clearwater Forest processor, add it to QEMU as it does not need any
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specific enablement.
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See https://lore.kernel.org/kvm/20241105054825.870939-1-tao1.su@linux.intel.com/
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for reference.
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Intel-SIG: commit 78be258c0eeb target/i386: add sha512, sm3, sm4 feature bits.
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Reviewed-by: Tao Su <tao1.su@linux.intel.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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[ Quanxian Wang: amend commit log ]
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Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
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---
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target/i386/cpu.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index b5231432e7..6ed4e84b5c 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -962,7 +962,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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[FEAT_7_1_EAX] = {
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.type = CPUID_FEATURE_WORD,
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.feat_names = {
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- NULL, NULL, NULL, NULL,
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+ "sha512", "sm3", "sm4", NULL,
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"avx-vnni", "avx512-bf16", NULL, "cmpccxadd",
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NULL, NULL, "fzrm", "fsrs",
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"fsrc", NULL, NULL, NULL,
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--
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2.41.0.windows.1
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