49 lines
1.5 KiB
Diff
49 lines
1.5 KiB
Diff
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From 3323c09d283e02c10bbf6e8dfc43ea9f41e746db Mon Sep 17 00:00:00 2001
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From: Lei Wang <lei4.wang@intel.com>
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Date: Wed, 24 Apr 2024 03:29:12 -0400
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Subject: [PATCH] target/i386: Introduce SapphireRapids-v3 to add missing
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features
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commit b10b2481738304db13d28252e86c10555121a5b3 upstream.
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Add the missing features(ss, tsc-adjust, cldemote, movdiri, movdir64b) in
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the SapphireRapids-v3 CPU model.
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Intel-SIG: commit b10b24817383 target/i386: Introduce SapphireRapids-v3 to add missing features.
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8.2-SPR new model support
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Signed-off-by: Lei Wang <lei4.wang@intel.com>
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Message-ID: <20240424072912.43188-1-lei4.wang@intel.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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[ Quanxian Wang: amend commit log ]
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Signed-off-by: Quanxian Wang <quanxian.wang@intel.com>
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---
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target/i386/cpu.c | 11 +++++++++++
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1 file changed, 11 insertions(+)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index 19ebd49e8c..ca7e5337b0 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -4020,6 +4020,17 @@ static const X86CPUDefinition builtin_x86_defs[] = {
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{ /* end of list */ }
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}
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},
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+ {
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+ .version = 3,
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+ .props = (PropValue[]) {
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+ { "ss", "on" },
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+ { "tsc-adjust", "on" },
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+ { "cldemote", "on" },
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+ { "movdiri", "on" },
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+ { "movdir64b", "on" },
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+ { /* end of list */ }
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+ }
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+ },
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{ /* end of list */ }
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}
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},
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--
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2.41.0.windows.1
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