40 lines
1.3 KiB
Diff
40 lines
1.3 KiB
Diff
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From b44fc9f3fc91363c55f6ba739f6c09222f979d88 Mon Sep 17 00:00:00 2001
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From: Sergey Makarov <s.makarov@syntacore.com>
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Date: Wed, 18 Sep 2024 17:02:29 +0300
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Subject: [PATCH] hw/intc: Don't clear pending bits on IRQ lowering
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According to PLIC specification (chapter 5), there
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is only one case, when interrupt is claimed. Fix
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PLIC controller to match this behavior.
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Signed-off-by: Sergey Makarov <s.makarov@syntacore.com>
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Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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Message-ID: <20240918140229.124329-3-s.makarov@syntacore.com>
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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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(cherry picked from commit a84be2baa9eca8bc500f866ad943b8f63dc99adf)
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Signed-off-by: zhujun2 <zhujun2_yewu@cmss.chinamobile.com>
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---
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hw/intc/sifive_plic.c | 6 ++++--
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1 file changed, 4 insertions(+), 2 deletions(-)
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diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
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index 5522ede2cf..e5de52bc44 100644
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--- a/hw/intc/sifive_plic.c
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+++ b/hw/intc/sifive_plic.c
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@@ -349,8 +349,10 @@ static void sifive_plic_irq_request(void *opaque, int irq, int level)
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{
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SiFivePLICState *s = opaque;
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- sifive_plic_set_pending(s, irq, level > 0);
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- sifive_plic_update(s);
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+ if (level > 0) {
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+ sifive_plic_set_pending(s, irq, true);
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+ sifive_plic_update(s);
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+ }
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}
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static void sifive_plic_realize(DeviceState *dev, Error **errp)
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--
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2.41.0.windows.1
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