From ad6ce039cab07b6a99ccaa36fbb0043ae85a74c9 Mon Sep 17 00:00:00 2001
From: Peng Liang <liangpeng10@huawei.com>
Date: Mon, 21 Sep 2020 22:14:20 +0800
Subject: [PATCH] target/arm: clear EL2 and EL3 only when kvm is not enabled

When has_el2 and has_el3 are disabled, which is the default value for
virt machine, QEMU will clear the corresponding field in ID_PFR1_EL1 and
ID_AA64PFR0_EL1 to not expose EL3 and EL2 to guest.  Because KVM doesn't
support to emulate ID registers in AArch64 before, it will not take
effect.  Hence, clear EL2 and EL3 only when kvm is not enabled for
backwards compatibility.

Signed-off-by: Peng Liang <liangpeng10@huawei.com>
---
 target/arm/cpu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 7ae2d3da56..3f62336acf 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1996,7 +1996,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
         }
     }
 
-    if (!cpu->has_el3) {
+    if (!cpu->has_el3 && !kvm_enabled()) {
         /* If the has_el3 CPU property is disabled then we need to disable the
          * feature.
          */
@@ -2037,7 +2037,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
         cpu->pmceid1 = 0;
     }
 
-    if (!arm_feature(env, ARM_FEATURE_EL2)) {
+    if (!arm_feature(env, ARM_FEATURE_EL2) && !kvm_enabled()) {
         /* Disable the hypervisor feature bits in the processor feature
          * registers if we don't have EL2. These are id_pfr1[15:12] and
          * id_aa64pfr0_el1[11:8].
-- 
2.23.0

