diff -ruN papi-6.0.0/src/libpfm4/config.mk papi/src/libpfm4/config.mk
--- papi-6.0.0/src/libpfm4/config.mk	2022-10-29 13:04:32.000000000 +0800
+++ papi/src/libpfm4/config.mk	2023-01-15 21:16:16.101680541 +0800
@@ -177,6 +177,9 @@
 CONFIG_PFMLIB_CELL=y
 endif
 
+ifeq ($(ARCH),riscv64)
+CONFIG_PFMLIB_ARCH_RISCV64=y
+endif
 
 #
 # you shouldn't have to touch anything beyond this point
diff -ruN papi-6.0.0/src/linux-context.h papi/src/linux-context.h
--- papi-6.0.0/src/linux-context.h	2022-10-29 13:04:32.000000000 +0800
+++ papi/src/linux-context.h	2023-01-15 21:16:16.101680541 +0800
@@ -37,6 +37,8 @@
 #define OVERFLOW_ADDRESS(ctx) ctx.ucontext->uc_mcontext.pc
 #elif defined(__hppa__)
 #define OVERFLOW_ADDRESS(ctx) ctx.ucontext->uc_mcontext.sc_iaoq[0]
+#elif defined(__riscv)
+#define OVERFLOW_ADDRESS(ctx) ctx.ucontext->uc_mcontext.__gregs[REG_PC]
 #else
 #error "OVERFLOW_ADDRESS() undefined!"
 #endif
diff -ruN papi-6.0.0/src/linux-timer.c papi/src/linux-timer.c
--- papi-6.0.0/src/linux-timer.c	2022-10-29 13:04:32.000000000 +0800
+++ papi/src/linux-timer.c	2023-01-15 21:16:16.101680541 +0800
@@ -288,6 +288,27 @@
   return 0;
 }
 
+/************************/
+/* riscv64 get_cycles() */
+/************************/
+
+#elif defined(__riscv) && defined(__riscv_xlen) && __riscv_xlen == 64
+static inline long long
+get_cycles( void )
+{
+	register unsigned long ret;
+
+	__asm__ __volatile__ ("rdcycle %0" : "=r" (ret));
+
+	return ret;
+}
+
+/*
+ * TODO: riscv32 implementation can be done following example in:
+ * Volume I: RISC-V User-Level ISA V2.2
+ *   2.8 Control and Status Register Instructions
+ *     Timers and Counters
+ */
 
 #elif !defined(HAVE_GETTIMEOFDAY) && !defined(HAVE_CLOCK_GETTIME)
 #error "No get_cycles support for this architecture. "
diff -ruN papi-6.0.0/src/mb.h papi/src/mb.h
--- papi-6.0.0/src/mb.h	2022-10-29 13:04:32.000000000 +0800
+++ papi/src/mb.h	2023-01-15 21:16:16.101680541 +0800
@@ -39,6 +39,9 @@
 #elif defined(__aarch64__)
 #define rmb()           asm volatile("dmb ld" ::: "memory")
 
+#elif defined(__riscv)
+#define rmb()           asm volatile("fence ir, ir" ::: "memory")
+
 #elif defined(__mips__)
 #define rmb()           asm volatile(                                   \
                                 ".set   mips2\n\t"                      \