From 1013f0b0b911d24eed216485767ec6eb080afa81 Mon Sep 17 00:00:00 2001 From: Ludovic Henry Date: Mon, 25 Sep 2023 08:01:45 +0000 Subject: [PATCH] 8316859: RISC-V: Disable detection of V through HWCAP --- .../os_cpu/linux_riscv/vm_version_linux_riscv.cpp | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/src/hotspot/os_cpu/linux_riscv/vm_version_linux_riscv.cpp b/src/hotspot/os_cpu/linux_riscv/vm_version_linux_riscv.cpp index 454ffbb06d390..69bbf9f366b31 100644 --- a/src/hotspot/os_cpu/linux_riscv/vm_version_linux_riscv.cpp +++ b/src/hotspot/os_cpu/linux_riscv/vm_version_linux_riscv.cpp @@ -149,12 +149,21 @@ void VM_Version::setup_cpu_available_features() { void VM_Version::os_aux_features() { uint64_t auxv = getauxval(AT_HWCAP); - int i = 0; - while (_feature_list[i] != nullptr) { + for (int i = 0; _feature_list[i] != nullptr; i++) { + if (_feature_list[i]->feature_bit() == HWCAP_ISA_V) { + // Special case for V: some dev boards only support RVV version 0.7, while + // the OpenJDK only supports RVV version 1.0. These two versions are not + // compatible with each other. Given the V bit is set through HWCAP on + // some custom kernels, regardless of the version, it can lead to + // generating V instructions on boards that don't support RVV version 1.0 + // (ex: Sipeed LicheePi), leading to a SIGILL. + // That is an acceptable workaround as only Linux Kernel v6.5+ supports V, + // and that version already support hwprobe anyway + continue; + } if ((_feature_list[i]->feature_bit() & auxv) != 0) { _feature_list[i]->enable_feature(); } - i++; } }