59 lines
1.8 KiB
Diff
59 lines
1.8 KiB
Diff
From e8bf6d9c5a02b3ffaf223dd1109bc15c664cca28 Mon Sep 17 00:00:00 2001
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Date: Mon, 24 Feb 2020 18:51:09 +0800
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Subject: [PATCH] ZGC: aarch64: fix not using load/store Pre-indexed
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addressing to modify sp
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Summary: <gc>: <instruction load/store Pre-indexed addressing offset range is not enough>
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LLT: JFUZZ
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Bug url:
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---
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src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp | 16 +++++-----------
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1 file changed, 5 insertions(+), 11 deletions(-)
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diff --git a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp
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index a65a605d0..6db979b57 100644
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--- a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp
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+++ b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp
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@@ -2114,12 +2114,11 @@ int MacroAssembler::push_fp(unsigned int bitset, Register stack) {
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return 0;
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}
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+ add(stack, stack, -count * wordSize * 2);
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+
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if (count & 1) {
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- strq(as_FloatRegister(regs[0]), Address(pre(stack, -count * wordSize * 2)));
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+ strq(as_FloatRegister(regs[0]), Address(stack));
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i += 1;
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- } else {
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- stpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(pre(stack, -count * wordSize * 2)));
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- i += 2;
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}
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for (; i < count; i += 2) {
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@@ -2145,20 +2144,15 @@ int MacroAssembler::pop_fp(unsigned int bitset, Register stack) {
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}
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if (count & 1) {
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+ ldrq(as_FloatRegister(regs[0]), Address(stack));
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i += 1;
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- } else {
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- i += 2;
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}
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for (; i < count; i += 2) {
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ldpq(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize * 2));
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}
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- if ((count & 1) == 0) {
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- ldpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(post(stack, count * wordSize * 2)));
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- } else {
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- ldrq(as_FloatRegister(regs[0]), Address(post(stack, count * wordSize * 2)));
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- }
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+ add(stack, stack, count * wordSize * 2);
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return count;
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}
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--
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2.12.3
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