From e8bf6d9c5a02b3ffaf223dd1109bc15c664cca28 Mon Sep 17 00:00:00 2001
Date: Mon, 24 Feb 2020 18:51:09 +0800
Subject: [PATCH] ZGC: aarch64: fix not using load/store Pre-indexed
 addressing to modify sp

Summary: <gc>: <instruction load/store Pre-indexed addressing offset range is not enough>
LLT: JFUZZ
Bug url:
---
 src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp | 16 +++++-----------
 1 file changed, 5 insertions(+), 11 deletions(-)

diff --git a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp
index a65a605d0..6db979b57 100644
--- a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp
+++ b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp
@@ -2114,12 +2114,11 @@ int MacroAssembler::push_fp(unsigned int bitset, Register stack) {
     return 0;
   }
 
+  add(stack, stack, -count * wordSize * 2);
+
   if (count & 1) {
-    strq(as_FloatRegister(regs[0]), Address(pre(stack, -count * wordSize * 2)));
+    strq(as_FloatRegister(regs[0]), Address(stack));
     i += 1;
-  } else {
-    stpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(pre(stack, -count * wordSize * 2)));
-    i += 2;
   }
 
   for (; i < count; i += 2) {
@@ -2145,20 +2144,15 @@ int MacroAssembler::pop_fp(unsigned int bitset, Register stack) {
   }
 
   if (count & 1) {
+    ldrq(as_FloatRegister(regs[0]), Address(stack));
     i += 1;
-  } else {
-    i += 2;
   }
 
   for (; i < count; i += 2) {
     ldpq(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize * 2));
   }
 
-  if ((count & 1) == 0) {
-    ldpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(post(stack, count * wordSize * 2)));
-  } else {
-    ldrq(as_FloatRegister(regs[0]), Address(post(stack, count * wordSize * 2)));
-  }
+  add(stack, stack, count * wordSize * 2);
 
   return count;
 }
-- 
2.12.3