!84 I3R9YJ: update to JDK11.0.11

From: @hu_bo_dao
Reviewed-by: @jvmboy
Signed-off-by: @jvmboy

8209894-ZGC-Cap-number-of-GC-workers-based-on-heap-s.patch

@@ -73,13 +73,6 @@ diff --git a/src/hotspot/share/gc/z/zWorkers.hpp b/src/hotspot/share/gc/z/zWorke
 index 36a3c61fd..6ce09c447 100644
 --- a/src/hotspot/share/gc/z/zWorkers.hpp
 +++ b/src/hotspot/share/gc/z/zWorkers.hpp
-@@ -1,5 +1,5 @@
- /*
-- * Copyright (c) 2015, 2017, Oracle and/or its affiliates. All rights reserved.
-+ * Copyright (c) 2015, 2018, Oracle and/or its affiliates. All rights reserved.
-  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
-  *
-  * This code is free software; you can redistribute it and/or modify it
 @@ -34,8 +34,6 @@ private:
    bool     _boost;
    WorkGang _workers;

8214535-support-Jmap-parallel.patch

@@ -61,8 +61,8 @@ index 7e9c6254c..fd2da14a3 100644
 +  heap_region_par_iterate_from_worker_offset(&blk, claimer, worker_id);
 +}
 +
- void G1CollectedHeap::heap_region_iterate(HeapRegionClosure* cl) const {
+ void G1CollectedHeap::keep_alive(oop obj) {
-   _hrm.iterate(cl);
+   G1BarrierSet::enqueue(obj);
  }
 diff --git a/src/hotspot/share/gc/g1/g1CollectedHeap.hpp b/src/hotspot/share/gc/g1/g1CollectedHeap.hpp
 index bb46cae83..82f59d69b 100644

8237483-AArch64-C1-OopMap-inserted-twice-fatal-error.patch

@@ -1,18 +0,0 @@
-diff --git a/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp b/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp
-index 82abda9..df3addf 100644
---- a/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp
-+++ b/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp
-@@ -2045,6 +2045,13 @@ void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmit
- 
-   // get current pc information
-   // pc is only needed if the method has an exception handler, the unwind code does not need it.
-+  if (compilation()->debug_info_recorder()->last_pc_offset() == __ offset()) {
-+    // As no instructions have been generated yet for this LIR node it's
-+    // possible that an oop map already exists for the current offset.
-+    // In that case insert an dummy NOP here to ensure all oop map PCs
-+    // are unique. See JDK-8237483.
-+    __ nop();
-+  }
-   int pc_for_athrow_offset = __ offset();
-   InternalAddress pc_for_athrow(__ pc());
-   __ adr(exceptionPC->as_register(), pc_for_athrow);

8240353.patch

@@ -1,65 +0,0 @@
-commit 29fd7a83a66269e360af353c64d945612be62623
-Date:   Thu Feb 4 16:37:53 2021 +0800
-
-    8240353: AArch64: missing support for -XX:+ExtendedDTraceProbes in C1
-    
-    Summary: <c1>: java -XX:+ExtendedDTraceProbes throws SIGILL
-    LLT: java -XX:+ExtendedDTraceProbes
-    Patch Type: backport
-    Bug url: https://bugs.openjdk.java.net/browse/JDK-8240353
-
-diff --git a/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp b/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp
-index 7798aa509..a8e89cde0 100644
---- a/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp
-+++ b/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp
-@@ -1,5 +1,5 @@
- /*
-- * Copyright (c) 2000, 2019, Oracle and/or its affiliates. All rights reserved.
-+ * Copyright (c) 2000, 2020, Oracle and/or its affiliates. All rights reserved.
-  * Copyright (c) 2014, Red Hat Inc. All rights reserved.
-  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
-  *
-@@ -449,12 +449,9 @@ int LIR_Assembler::emit_unwind_handler() {
-   }
- 
-   if (compilation()->env()->dtrace_method_probes()) {
--    __ call_Unimplemented();
--#if 0
--    __ movptr(Address(rsp, 0), rax);
--    __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());
--    __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
--#endif
-+    __ mov(c_rarg0, rthread);
-+    __ mov_metadata(c_rarg1, method()->constant_encoding());
-+    __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1);
-   }
- 
-   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
-diff --git a/src/hotspot/cpu/aarch64/c1_Runtime1_aarch64.cpp b/src/hotspot/cpu/aarch64/c1_Runtime1_aarch64.cpp
-index 2344e0be3..3f5ab6641 100644
---- a/src/hotspot/cpu/aarch64/c1_Runtime1_aarch64.cpp
-+++ b/src/hotspot/cpu/aarch64/c1_Runtime1_aarch64.cpp
-@@ -1,5 +1,5 @@
- /*
-- * Copyright (c) 1999, 2018, Oracle and/or its affiliates. All rights reserved.
-+ * Copyright (c) 1999, 2020, Oracle and/or its affiliates. All rights reserved.
-  * Copyright (c) 2014, Red Hat Inc. All rights reserved.
-  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
-  *
-@@ -1123,6 +1123,16 @@ OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
-       }
-       break;
- 
-+    case dtrace_object_alloc_id:
-+      { // c_rarg0: object
-+        StubFrame f(sasm, "dtrace_object_alloc", dont_gc_arguments);
-+        save_live_registers(sasm);
-+
-+        __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_object_alloc), c_rarg0);
-+
-+        restore_live_registers(sasm);
-+      }
-+      break;
- 
-     default:
-       { StubFrame f(sasm, "unimplemented entry", dont_gc_arguments);

8243670-Unexpected-test-result-caused-by-C2-MergeMem.patch

@@ -1,170 +0,0 @@
-diff --git a/src/hotspot/share/opto/cfgnode.cpp b/src/hotspot/share/opto/cfgnode.cpp
-index 8c59efb..e32b5e7 100644
---- a/src/hotspot/share/opto/cfgnode.cpp
-+++ b/src/hotspot/share/opto/cfgnode.cpp
-@@ -1192,6 +1192,30 @@ Node* PhiNode::Identity(PhaseGVN* phase) {
-     if (id != NULL)  return id;
-   }
- 
-+  // Looking for phis with identical inputs.  If we find one that has
-+  // type TypePtr::BOTTOM, replace the current phi with the bottom phi.
-+  if (phase->is_IterGVN() && type() == Type::MEMORY && adr_type() !=
-+      TypePtr::BOTTOM && !adr_type()->is_known_instance()) {
-+    uint phi_len = req();
-+    Node* phi_reg = region();
-+    for (DUIterator_Fast imax, i = phi_reg->fast_outs(imax); i < imax; i++) {
-+      Node* u = phi_reg->fast_out(i);
-+      if (u->is_Phi() && u->as_Phi()->type() == Type::MEMORY &&
-+          u->adr_type() == TypePtr::BOTTOM && u->in(0) == phi_reg &&
-+          u->req() == phi_len) {
-+        for (uint j = 1; j < phi_len; j++) {
-+          if (in(j) != u->in(j)) {
-+            u = NULL;
-+            break;
-+          }
-+        }
-+        if (u != NULL) {
-+          return u;
-+        }
-+      }
-+    }
-+  }
-+
-   return this;                     // No identity
- }
- 
-diff --git a/src/hotspot/share/opto/memnode.cpp b/src/hotspot/share/opto/memnode.cpp
-index 9e22011..bc314c0 100644
---- a/src/hotspot/share/opto/memnode.cpp
-+++ b/src/hotspot/share/opto/memnode.cpp
-@@ -4554,24 +4554,6 @@ Node *MergeMemNode::Ideal(PhaseGVN *phase, bool can_reshape) {
-     }
-     // else preceding memory was not a MergeMem
- 
--    // replace equivalent phis (unfortunately, they do not GVN together)
--    if (new_mem != NULL && new_mem != new_base &&
--        new_mem->req() == phi_len && new_mem->in(0) == phi_reg) {
--      if (new_mem->is_Phi()) {
--        PhiNode* phi_mem = new_mem->as_Phi();
--        for (uint i = 1; i < phi_len; i++) {
--          if (phi_base->in(i) != phi_mem->in(i)) {
--            phi_mem = NULL;
--            break;
--          }
--        }
--        if (phi_mem != NULL) {
--          // equivalent phi nodes; revert to the def
--          new_mem = new_base;
--        }
--      }
--    }
--
-     // maybe store down a new value
-     Node* new_in = new_mem;
-     if (new_in == new_base)  new_in = empty_mem;
-diff --git a/src/hotspot/share/opto/type.hpp b/src/hotspot/share/opto/type.hpp
-index 8103c6f..5928f44 100644
---- a/src/hotspot/share/opto/type.hpp
-+++ b/src/hotspot/share/opto/type.hpp
-@@ -453,6 +453,7 @@ public:
-   const Type* maybe_remove_speculative(bool include_speculative) const;
- 
-   virtual bool maybe_null() const { return true; }
-+  virtual bool is_known_instance() const { return false; }
- 
- private:
-   // support arrays
-@@ -1390,6 +1391,10 @@ public:
-     return _ptrtype;
-   }
- 
-+  bool is_known_instance() const {
-+    return _ptrtype->is_known_instance();
-+  }
-+
- #ifndef PRODUCT
-   virtual void dump2( Dict &d, uint depth, outputStream *st ) const;
- #endif
-diff --git a/test/hotspot/jtreg/compiler/c2/TestReplaceEquivPhis.java b/test/hotspot/jtreg/compiler/c2/TestReplaceEquivPhis.java
-new file mode 100644
-index 0000000..d4c93b3
---- /dev/null
-+++ b/test/hotspot/jtreg/compiler/c2/TestReplaceEquivPhis.java
-@@ -0,0 +1,77 @@
-+/*
-+ * Copyright (c) 2020, Huawei Technologies Co. Ltd. All rights reserved.
-+ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
-+ *
-+ * This code is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 only, as
-+ * published by the Free Software Foundation.
-+ *
-+ * This code is distributed in the hope that it will be useful, but WITHOUT
-+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-+ * version 2 for more details (a copy is included in the LICENSE file that
-+ * accompanied this code).
-+ *
-+ * You should have received a copy of the GNU General Public License version
-+ * 2 along with this work; if not, write to the Free Software Foundation,
-+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
-+ *
-+ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
-+ * or visit www.oracle.com if you need additional information or have any
-+ * questions.
-+ */
-+
-+/**
-+ * @test
-+ * @bug 8243670
-+ * @summary Unexpected test result caused by C2 MergeMemNode::Ideal
-+ *
-+ * @run main/othervm -Xcomp -XX:-SplitIfBlocks
-+ *      -XX:CompileOnly=compiler.c2.TestReplaceEquivPhis::test
-+ *      -XX:-BackgroundCompilation compiler.c2.TestReplaceEquivPhis
-+ */
-+
-+package compiler.c2;
-+
-+public class TestReplaceEquivPhis {
-+
-+    public static final int N = 400;
-+    public static volatile int instanceCount = 0;
-+    public int iFld = 0;
-+    public static int iArrFld[] = new int[N];
-+
-+    public int test() {
-+        int v = 0;
-+        boolean bArr[] = new boolean[N];
-+
-+        for (int i = 1; i < 344; i++) {
-+            iFld = i;
-+            for (int j = 2; j <177 ; j++) {
-+                v = iFld;
-+                iFld = TestReplaceEquivPhis.instanceCount;
-+                TestReplaceEquivPhis.iArrFld[i] = 0;
-+                iFld += TestReplaceEquivPhis.instanceCount;
-+                TestReplaceEquivPhis.iArrFld[i] = 0;
-+                bArr[j] = false;
-+                TestReplaceEquivPhis.instanceCount = 1;
-+
-+                for (int k = 1; k < 3; k++) {
-+                    // do nothing
-+                }
-+            }
-+        }
-+        return v;
-+    }
-+
-+    public static void main(String[] args) {
-+            TestReplaceEquivPhis obj = new TestReplaceEquivPhis();
-+            for (int i = 0; i < 5; i++) {
-+                int result = obj.test();
-+                if (result != 2) {
-+                    throw new RuntimeException("Test failed.");
-+                }
-+            }
-+            System.out.println("Test passed.");
-+    }
-+
-+}

8247766-aarch64-guarantee-val-1U--nbits-failed-Field-too-big-for-insn.patch

@@ -1,257 +0,0 @@
-diff --git a/src/hotspot/cpu/aarch64/assembler_aarch64.hpp b/src/hotspot/cpu/aarch64/assembler_aarch64.hpp
-index db582f25f..80ddb9b31 100644
---- a/src/hotspot/cpu/aarch64/assembler_aarch64.hpp
-+++ b/src/hotspot/cpu/aarch64/assembler_aarch64.hpp
-@@ -553,14 +553,7 @@ class Address {
- 
-   void lea(MacroAssembler *, Register) const;
- 
--  static bool offset_ok_for_immed(long offset, int shift = 0) {
--    unsigned mask = (1 << shift) - 1;
--    if (offset < 0 || offset & mask) {
--      return (uabs(offset) < (1 << (20 - 12))); // Unscaled offset
--    } else {
--      return ((offset >> shift) < (1 << (21 - 10 + 1))); // Scaled, unsigned offset
--    }
--  }
-+  static bool offset_ok_for_immed(long offset, uint shift);
- };
- 
- // Convience classes
-diff --git a/src/hotspot/cpu/aarch64/assembler_aarch64.inline.hpp b/src/hotspot/cpu/aarch64/assembler_aarch64.inline.hpp
-index 86eb8c2f8..a475575bf 100644
---- a/src/hotspot/cpu/aarch64/assembler_aarch64.inline.hpp
-+++ b/src/hotspot/cpu/aarch64/assembler_aarch64.inline.hpp
-@@ -30,4 +30,15 @@
- #include "asm/codeBuffer.hpp"
- #include "code/codeCache.hpp"
- 
-+inline bool Address::offset_ok_for_immed(long offset, uint shift = 0) {
-+  uint mask = (1 << shift) - 1;
-+  if (offset < 0 || (offset & mask) != 0) {
-+    // Unscaled signed offset, encoded in a signed imm9 field.
-+    return Assembler::is_simm9(offset);
-+  } else {
-+    // Scaled unsigned offset, encoded in an unsigned imm12:_ field.
-+    return Assembler::is_uimm12(offset >> shift);
-+  }
-+}
-+
- #endif // CPU_AARCH64_VM_ASSEMBLER_AARCH64_INLINE_HPP
-diff --git a/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp b/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp
-index f6a77dc78..7798aa509 100644
---- a/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp
-+++ b/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp
-@@ -226,6 +226,19 @@ Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
-   // FIXME: This needs to be much more clever.  See x86.
- }
- 
-+// Ensure a valid Address (base + offset) to a stack-slot. If stack access is
-+// not encodable as a base + (immediate) offset, generate an explicit address
-+// calculation to hold the address in a temporary register.
-+Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) {
-+  precond(size == 4 || size == 8);
-+  Address addr = frame_map()->address_for_slot(index, adjust);
-+  precond(addr.getMode() == Address::base_plus_offset);
-+  precond(addr.base() == sp);
-+  precond(addr.offset() > 0);
-+  uint mask = size - 1;
-+  assert((addr.offset() & mask) == 0, "scaled offsets only");
-+  return __ legitimize_address(addr, size, tmp);
-+}
- 
- void LIR_Assembler::osr_entry() {
-   offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
-@@ -745,32 +758,38 @@ void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
- }
- 
- void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
-+  precond(src->is_register() && dest->is_stack());
-+
-+  uint const c_sz32 = sizeof(uint32_t);
-+  uint const c_sz64 = sizeof(uint64_t);
-+
-   if (src->is_single_cpu()) {
-+    int index = dest->single_stack_ix();
-     if (type == T_ARRAY || type == T_OBJECT) {
--      __ str(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix()));
-+      __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
-       __ verify_oop(src->as_register());
-     } else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) {
--      __ str(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix()));
-+      __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
-     } else {
--      __ strw(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix()));
-+      __ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1));
-     }
- 
-   } else if (src->is_double_cpu()) {
--    Address dest_addr_LO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
-+    int index = dest->double_stack_ix();
-+    Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
-     __ str(src->as_register_lo(), dest_addr_LO);
- 
-   } else if (src->is_single_fpu()) {
--    Address dest_addr = frame_map()->address_for_slot(dest->single_stack_ix());
--    __ strs(src->as_float_reg(), dest_addr);
-+    int index = dest->single_stack_ix();
-+    __ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
- 
-   } else if (src->is_double_fpu()) {
--    Address dest_addr = frame_map()->address_for_slot(dest->double_stack_ix());
--    __ strd(src->as_double_reg(), dest_addr);
-+    int index = dest->double_stack_ix();
-+    __ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
- 
-   } else {
-     ShouldNotReachHere();
-   }
--
- }
- 
- 
-@@ -855,32 +874,34 @@ void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_Patch
- 
- 
- void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
--  assert(src->is_stack(), "should not call otherwise");
--  assert(dest->is_register(), "should not call otherwise");
-+  precond(src->is_stack() && dest->is_register());
-+
-+  uint const c_sz32 = sizeof(uint32_t);
-+  uint const c_sz64 = sizeof(uint64_t);
- 
-   if (dest->is_single_cpu()) {
-+    int index = src->single_stack_ix();
-     if (type == T_ARRAY || type == T_OBJECT) {
--      __ ldr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
-+      __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
-       __ verify_oop(dest->as_register());
-     } else if (type == T_METADATA || type == T_ADDRESS) {
--      __ ldr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
-+      __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
-     } else {
--      Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
--      Address data_addr = __ form_address(rscratch1, sp, src_addr.offset(), 2);
--      __ ldrw(dest->as_register(), data_addr);
-+      __ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1));
-     }
- 
-   } else if (dest->is_double_cpu()) {
--    Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
-+    int index = src->double_stack_ix();
-+    Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
-     __ ldr(dest->as_register_lo(), src_addr_LO);
- 
-   } else if (dest->is_single_fpu()) {
--    Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
--    __ ldrs(dest->as_float_reg(), src_addr);
-+    int index = src->single_stack_ix();
-+    __ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
- 
-   } else if (dest->is_double_fpu()) {
--    Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
--    __ ldrd(dest->as_double_reg(), src_addr);
-+    int index = src->double_stack_ix();
-+    __ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
- 
-   } else {
-     ShouldNotReachHere();
-diff --git a/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.hpp b/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.hpp
-index 6374a33e6..9db81fed9 100644
---- a/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.hpp
-+++ b/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.hpp
-@@ -45,10 +45,12 @@ friend class ArrayCopyStub;
- 
-   bool is_literal_address(LIR_Address* addr);
- 
--  // When we need to use something other than rscratch1 use this
--  // method.
-+  // When we need to use something other than rscratch1 use this method.
-   Address as_Address(LIR_Address* addr, Register tmp);
- 
-+  // Ensure we have a valid Address (base+offset) to a stack-slot.
-+  Address stack_slot_address(int index, uint shift, Register tmp, int adjust = 0);
-+
-   // Record the type of the receiver in ReceiverTypeData
-   void type_profile_helper(Register mdo,
-                            ciMethodData *md, ciProfileData *data,
-diff --git a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp
-index 44497ea7c..014a4d3c6 100644
---- a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp
-+++ b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp
-@@ -26,7 +26,7 @@
- #ifndef CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
- #define CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
- 
--#include "asm/assembler.hpp"
-+#include "asm/assembler.inline.hpp"
- 
- // MacroAssembler extends Assembler by frequently used macros.
- //
-@@ -132,6 +132,20 @@ class MacroAssembler: public Assembler {
-     a.lea(this, r);
-   }
- 
-+  /* Sometimes we get misaligned loads and stores, usually from Unsafe
-+     accesses, and these can exceed the offset range. */
-+  Address legitimize_address(const Address &a, int size, Register scratch) {
-+    if (a.getMode() == Address::base_plus_offset) {
-+      if (! Address::offset_ok_for_immed(a.offset(), exact_log2(size))) {
-+        block_comment("legitimize_address {");
-+        lea(scratch, a);
-+        block_comment("} legitimize_address");
-+        return Address(scratch);
-+      }
-+    }
-+    return a;
-+  }
-+
-   void addmw(Address a, Register incr, Register scratch) {
-     ldrw(scratch, a);
-     addw(scratch, scratch, incr);
-diff --git a/src/hotspot/share/asm/assembler.hpp b/src/hotspot/share/asm/assembler.hpp
-index da181b90b..56c3068e4 100644
---- a/src/hotspot/share/asm/assembler.hpp
-+++ b/src/hotspot/share/asm/assembler.hpp
-@@ -302,6 +302,7 @@ class AbstractAssembler : public ResourceObj  {
-   // Define some:
-   static bool is_simm5( intptr_t x) { return is_simm(x, 5 ); }
-   static bool is_simm8( intptr_t x) { return is_simm(x, 8 ); }
-+  static bool is_simm9( intptr_t x) { return is_simm(x, 9 ); }
-   static bool is_simm10(intptr_t x) { return is_simm(x, 10); }
-   static bool is_simm11(intptr_t x) { return is_simm(x, 11); }
-   static bool is_simm12(intptr_t x) { return is_simm(x, 12); }
-@@ -310,6 +311,15 @@ class AbstractAssembler : public ResourceObj  {
-   static bool is_simm26(intptr_t x) { return is_simm(x, 26); }
-   static bool is_simm32(intptr_t x) { return is_simm(x, 32); }
- 
-+  // Test if x is within unsigned immediate range for width.
-+  static bool is_uimm(intptr_t x, uint w) {
-+    precond(0 < w && w < 64);
-+    intptr_t limes = intptr_t(1) << w;
-+    return x < limes;
-+  }
-+
-+  static bool is_uimm12(intptr_t x) { return is_uimm(x, 12); }
-+
-   // Accessors
-   CodeSection*  code_section() const   { return _code_section; }
-   CodeBuffer*   code()         const   { return code_section()->outer(); }
-diff --git a/src/hotspot/share/utilities/debug.hpp b/src/hotspot/share/utilities/debug.hpp
-index aa594754a..c66c710f2 100644
---- a/src/hotspot/share/utilities/debug.hpp
-+++ b/src/hotspot/share/utilities/debug.hpp
-@@ -66,6 +66,9 @@ do {                                                                           \
- // For backward compatibility.
- #define assert(p, ...) vmassert(p, __VA_ARGS__)
- 
-+#define precond(p)   assert(p, "precond")
-+#define postcond(p)  assert(p, "postcond")
-+
- #ifndef ASSERT
- #define vmassert_status(p, status, msg)
- #else
--- 
-2.19.1
-

8248336-AArch64-C2-offset-overflow-in-BoxLockNode-em.patch

@@ -1,45 +0,0 @@
-From 3070d796490221304ef226560ad2a837c3de4401 Mon Sep 17 00:00:00 2001
-Date: Sat, 31 Oct 2020 14:17:53 +0800
-Subject: [PATCH] 8248336: AArch64: C2: offset overflow in BoxLockNode::emit
-
-Summary: <C2>: offset overflow in BoxLockNode::emit
-LLT: jtreg
-Bug url: https://bugs.openjdk.java.net/browse/JDK-8248336
----
- src/hotspot/cpu/aarch64/aarch64.ad | 16 ++++++++++------
- 1 file changed, 10 insertions(+), 6 deletions(-)
-
-diff --git a/src/hotspot/cpu/aarch64/aarch64.ad b/src/hotspot/cpu/aarch64/aarch64.ad
-index 827ec9e..617b2b8 100644
---- a/src/hotspot/cpu/aarch64/aarch64.ad
-+++ b/src/hotspot/cpu/aarch64/aarch64.ad
-@@ -2071,16 +2071,20 @@ void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
-   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
-   int reg    = ra_->get_encode(this);
- 
--  if (Assembler::operand_valid_for_add_sub_immediate(offset)) {
--    __ add(as_Register(reg), sp, offset);
--  } else {
--    ShouldNotReachHere();
--  }
-+  // This add will handle any 24-bit signed offset. 24 bits allows an
-+  // 8 megabyte stack frame.
-+  __ add(as_Register(reg), sp, offset);
- }
- 
- uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
-   // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
--  return 4;
-+  int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
-+
-+  if (Assembler::operand_valid_for_add_sub_immediate(offset)) {
-+    return NativeInstruction::instruction_size;
-+  } else {
-+    return 2 * NativeInstruction::instruction_size;
-+  }
- }
- 
- //=============================================================================
--- 
-1.8.3.1
-

add-SVE-backend-feature.patch

@@ -5558,11 +5558,11 @@ index 80ddb9b31..f554b5e15 100644
 +
    unsigned get(int msb = 31, int lsb = 0) {
      int nbits = msb - lsb + 1;
-     unsigned mask = ((1U << nbits) - 1) << lsb;
+     unsigned mask = checked_cast<unsigned>(right_n_bits(nbits)) << lsb;
 @@ -554,6 +565,18 @@ class Address {
    void lea(MacroAssembler *, Register) const;
  
-   static bool offset_ok_for_immed(long offset, uint shift);
+   static bool offset_ok_for_immed(int64_t offset, uint shift = 0);
 +
 +  static bool offset_ok_for_sve_immed(long offset, int shift, int vl /* sve vector length */) {
 +    if (offset % vl == 0) {

address-s-offset-may-exceed-the-limit-of-ldrw-instru.patch

@@ -1,31 +0,0 @@
-From c98fac94c7ce8826dec848d38723eebb192600f1 Mon Sep 17 00:00:00 2001
-Date: Tue, 21 Apr 2020 15:54:35 +0800
-Subject: [PATCH] address's offset may exceed the limit of ldrw instruction in
- stack2reg
-
-Summary: <c1>: <for 32-bit variant ldr, imm12 field is from 0 to 16380>
-LLT: test/hotspot/jtreg/runtime/handshake/HandshakeWalkSuspendExitTest.java
-Bug url: NA
-d31f3a48
----
- src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
-diff --git a/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp b/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp
-index cf3ce0a..82abda9 100644
---- a/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp
-+++ b/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp
-@@ -864,7 +864,9 @@ void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
-     } else if (type == T_METADATA || type == T_ADDRESS) {
-       __ ldr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
-     } else {
--      __ ldrw(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
-+      Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
-+      Address data_addr = __ form_address(rscratch1, sp, src_addr.offset(), 2);
-+      __ ldrw(dest->as_register(), data_addr);
-     }
- 
-   } else if (dest->is_double_cpu()) {
--- 
-1.8.3.1
-

java-11-openjdk.spec

@@ -114,7 +114,7 @@
 
 # New Version-String scheme-style defines
 %global majorver 11
-%global securityver 10
+%global securityver 11
 # buildjdkver is usually same as %%{majorver},
 # but in time of bootstrap of next jdk, it is majorver-1,
 # and this it is better to change it here, on single place
@@ -135,7 +135,7 @@
 
 %global project		jdk-updates
 %global repo		jdk11u
-%global revision	jdk-11.0.10-ga
+%global revision	jdk-11.0.11-ga
 %global full_revision %{project}-%{repo}-%{revision}
 # priority must be 7 digits in total
 # setting to 1, so debug ones can have 0
@@ -740,7 +740,7 @@ Provides: java-src%{?1} = %{epoch}:%{version}-%{release}
 
 Name:    java-%{javaver}-%{origin}
 Version: %{newjavaver}.%{buildver}
-Release: 8
+Release: 0
 # java-1.5.0-ibm from jpackage.org set Epoch to 1 for unknown reasons
 # and this change was brought into RHEL-4. java-1.5.0-ibm packages
 # also included the epoch in their virtual provides. This created a
@@ -816,7 +816,6 @@ Patch22: 8233506-ZGC-the-load-for-Reference.get-can-be-conver.patch
 Patch23: add-missing-inline.patch
 Patch26: ZGC-aarch64-fix-system-call-number-of-memfd_create.patch
 Patch27: ZGC-aarch64-fix-not-using-load-store-Pre-index.patch
-Patch28: address-s-offset-may-exceed-the-limit-of-ldrw-instru.patch
 Patch29: ZGC-reuse-entries-of-ResolvedMethodTable.patch
 
 # 11.0.8
@@ -829,24 +828,19 @@ Patch38: fast-serializer-jdk11.patch
 Patch39: fix-jck-failure-on-FastSerializer.patch
 Patch40: 8223667-ASAN-build-broken.patch
 Patch42: 8229496-SIGFPE-division-by-zero-in-C2-OSR-compiled-method.patch
-Patch43: 8243670-Unexpected-test-result-caused-by-C2-MergeMem.patch
 Patch45: leaf-optimize-in-ParallelScanvageGC.patch
 Patch46: ZGC-correct-free-heap-size-excluding-waste-in-rule_allocation_rate.patch
 Patch47: 8204947-Port-ShenandoahTaskTerminator-to-mainline-and-make-it-default.patch
 Patch48: 8205921-Optimizing-best_of_2-work-stealing-queue-selection.patch
-Patch49: 8237483-AArch64-C1-OopMap-inserted-twice-fatal-error.patch
-Patch50: 8248336-AArch64-C2-offset-overflow-in-BoxLockNode-em.patch
 
 # 11.0.9
 Patch54: 8207160-ClassReader-adjustMethodParams-can-potentially-return-null-if-the-args-list-is-empty.patch
 Patch55: 8215047-Task-terminators-do-not-complete-termination-in-consistent-state.patch
-Patch56: 8247766-aarch64-guarantee-val-1U--nbits-failed-Field-too-big-for-insn.patch
 Patch57: add-zgc-parameter-adaptation-feature.patch
 Patch58: add-integerCache-feature.patch
 Patch59: add-SVE-backend-feature.patch
 
 #11.0.10
-Patch60: 8240353.patch
 Patch61: downgrade-the-symver-of-log2f-posix-spawn.patch
 Patch62: 8254078-DataOutputStream-is-very-slow-post-disabling.patch
 Patch63: 8217918-C2-XX-AggressiveUnboxing-is-broken.patch
@@ -1101,7 +1095,6 @@ pushd %{top_level_dir_name}
 %patch23 -p1
 %patch26 -p1
 %patch27 -p1
-%patch28 -p1
 %patch29 -p1
 %patch33 -p1
 %patch34 -p1
@@ -1112,20 +1105,15 @@ pushd %{top_level_dir_name}
 %patch39 -p1
 %patch40 -p1
 %patch42 -p1
-%patch43 -p1
 %patch45 -p1
 %patch46 -p1
 %patch47 -p1
 %patch48 -p1
-%patch49 -p1
-%patch50 -p1
 %patch54 -p1
 %patch55 -p1
-%patch56 -p1
 %patch57 -p1
 %patch58 -p1
 %patch59 -p1
-%patch60 -p1
 %patch61 -p1
 %patch62 -p1
 %patch63 -p1
@@ -1638,6 +1626,9 @@ require "copy_jdk_configs.lua"
 
 
 %changelog
+* Fri May 14 2021 hu_bo_dao <hubodao@huawei.com> - 1:11.0.11.9-0
+- Update to 11.0.11+9 (GA)
+
 * Sat Apr 17 2021 aijm <aijiaming1@huawei.com> - 1:11.0.10.9-8
 - add G1-iterate-region-by-bitmap-rather-than-obj-size-in.patch
 

src-openeuler-openjdk-11-resolve-code-inconsistencies.patch

@@ -1002,8 +1002,8 @@ index 540f353e6..727b9b948 100644
              + File.separator + "security" + File.separator + "cacerts";
  
      // The numbers of certs now.
--    private static final int COUNT = 95;
+-    private static final int COUNT = 97;
-+    private static final int COUNT = 87;
++    private static final int COUNT = 89;
  
      // SHA-256 of cacerts, can be generated with
      // shasum -a 256 cacerts | sed -e 's/../&:/g' | tr '[:lower:]' '[:upper:]' | cut -c1-95