From 18161c97014b072d7c0628fada35f1ed050c7c78 Mon Sep 17 00:00:00 2001 From: wuyan Date: Thu, 16 Jan 2020 20:30:28 +0800 Subject: [PATCH] 8171410: aarch64: long multiplyExact shifts by 31 instead of 63 Summary: : long multiplyExact shifts by 31 instead of 63 LLT: NA Patch Type: backport Bug url: https://bugs.openjdk.java.net/browse/JDK-8171410 --- hotspot/src/cpu/aarch64/vm/aarch64.ad | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hotspot/src/cpu/aarch64/vm/aarch64.ad b/hotspot/src/cpu/aarch64/vm/aarch64.ad index a82629edda..b010a690c4 100644 --- a/hotspot/src/cpu/aarch64/vm/aarch64.ad +++ b/hotspot/src/cpu/aarch64/vm/aarch64.ad @@ -12438,7 +12438,7 @@ instruct overflowMulL_reg(rFlagsReg cr, iRegL op1, iRegL op2) format %{ "mul rscratch1, $op1, $op2\t#overflow check long\n\t" "smulh rscratch2, $op1, $op2\n\t" - "cmp rscratch2, rscratch1, ASR #31\n\t" + "cmp rscratch2, rscratch1, ASR #63\n\t" "movw rscratch1, #0x80000000\n\t" "cselw rscratch1, rscratch1, zr, NE\n\t" "cmpw rscratch1, #1" %} @@ -12446,7 +12446,7 @@ instruct overflowMulL_reg(rFlagsReg cr, iRegL op1, iRegL op2) ins_encode %{ __ mul(rscratch1, $op1$$Register, $op2$$Register); // Result bits 0..63 __ smulh(rscratch2, $op1$$Register, $op2$$Register); // Result bits 64..127 - __ cmp(rscratch2, rscratch1, Assembler::ASR, 31); // Top is pure sign ext + __ cmp(rscratch2, rscratch1, Assembler::ASR, 63); // Top is pure sign ext __ movw(rscratch1, 0x80000000); // Develop 0 (EQ), __ cselw(rscratch1, rscratch1, zr, Assembler::NE); // or 0x80000000 (NE) __ cmpw(rscratch1, 1); // 0x80000000 - 1 => VS @@ -12464,7 +12464,7 @@ instruct overflowMulL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, rF format %{ "mul rscratch1, $op1, $op2\t#overflow check long\n\t" "smulh rscratch2, $op1, $op2\n\t" - "cmp rscratch2, rscratch1, ASR #31\n\t" + "cmp rscratch2, rscratch1, ASR #63\n\t" "b$cmp $labl" %} ins_cost(4 * INSN_COST); // Branch is rare so treat as INSN_COST ins_encode %{ @@ -12472,7 +12472,7 @@ instruct overflowMulL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, rF Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode; __ mul(rscratch1, $op1$$Register, $op2$$Register); // Result bits 0..63 __ smulh(rscratch2, $op1$$Register, $op2$$Register); // Result bits 64..127 - __ cmp(rscratch2, rscratch1, Assembler::ASR, 31); // Top is pure sign ext + __ cmp(rscratch2, rscratch1, Assembler::ASR, 63); // Top is pure sign ext __ br(cond == Assembler::VS ? Assembler::NE : Assembler::EQ, *L); %} -- 2.12.3