56 lines
2.7 KiB
Diff
56 lines
2.7 KiB
Diff
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From 18161c97014b072d7c0628fada35f1ed050c7c78 Mon Sep 17 00:00:00 2001
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Date: Thu, 16 Jan 2020 20:30:28 +0800
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Subject: [PATCH] 8171410: aarch64: long multiplyExact shifts by 31 instead of
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63
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Summary: <c2>: long multiplyExact shifts by 31 instead of 63
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LLT: NA
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Bug url: https://bugs.openjdk.java.net/browse/JDK-8171410
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---
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hotspot/src/cpu/aarch64/vm/aarch64.ad | 8 ++++----
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1 file changed, 4 insertions(+), 4 deletions(-)
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diff --git a/hotspot/src/cpu/aarch64/vm/aarch64.ad b/hotspot/src/cpu/aarch64/vm/aarch64.ad
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index a82629edda..b010a690c4 100644
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--- a/hotspot/src/cpu/aarch64/vm/aarch64.ad
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+++ b/hotspot/src/cpu/aarch64/vm/aarch64.ad
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@@ -12438,7 +12438,7 @@ instruct overflowMulL_reg(rFlagsReg cr, iRegL op1, iRegL op2)
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format %{ "mul rscratch1, $op1, $op2\t#overflow check long\n\t"
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"smulh rscratch2, $op1, $op2\n\t"
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- "cmp rscratch2, rscratch1, ASR #31\n\t"
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+ "cmp rscratch2, rscratch1, ASR #63\n\t"
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"movw rscratch1, #0x80000000\n\t"
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"cselw rscratch1, rscratch1, zr, NE\n\t"
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"cmpw rscratch1, #1" %}
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@@ -12446,7 +12446,7 @@ instruct overflowMulL_reg(rFlagsReg cr, iRegL op1, iRegL op2)
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ins_encode %{
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__ mul(rscratch1, $op1$$Register, $op2$$Register); // Result bits 0..63
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__ smulh(rscratch2, $op1$$Register, $op2$$Register); // Result bits 64..127
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- __ cmp(rscratch2, rscratch1, Assembler::ASR, 31); // Top is pure sign ext
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+ __ cmp(rscratch2, rscratch1, Assembler::ASR, 63); // Top is pure sign ext
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__ movw(rscratch1, 0x80000000); // Develop 0 (EQ),
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__ cselw(rscratch1, rscratch1, zr, Assembler::NE); // or 0x80000000 (NE)
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__ cmpw(rscratch1, 1); // 0x80000000 - 1 => VS
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@@ -12464,7 +12464,7 @@ instruct overflowMulL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, rF
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format %{ "mul rscratch1, $op1, $op2\t#overflow check long\n\t"
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"smulh rscratch2, $op1, $op2\n\t"
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- "cmp rscratch2, rscratch1, ASR #31\n\t"
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+ "cmp rscratch2, rscratch1, ASR #63\n\t"
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"b$cmp $labl" %}
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ins_cost(4 * INSN_COST); // Branch is rare so treat as INSN_COST
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ins_encode %{
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@@ -12472,7 +12472,7 @@ instruct overflowMulL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, rF
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Assembler::Condition cond = (Assembler::Condition)$cmp$$cmpcode;
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__ mul(rscratch1, $op1$$Register, $op2$$Register); // Result bits 0..63
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__ smulh(rscratch2, $op1$$Register, $op2$$Register); // Result bits 64..127
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- __ cmp(rscratch2, rscratch1, Assembler::ASR, 31); // Top is pure sign ext
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+ __ cmp(rscratch2, rscratch1, Assembler::ASR, 63); // Top is pure sign ext
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__ br(cond == Assembler::VS ? Assembler::NE : Assembler::EQ, *L);
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%}
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--
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2.12.3
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