!15 Add riscv64 support

From: @misaka00251 Reviewed-by: @dillon_chen Signed-off-by: @dillon_chen
Add riscv64 support
2023-08-25 10:23:13 +00:00 · 2023-07-28 15:19:37 +08:00 · 2023-05-31 09:54:56 +00:00 · 2023-05-29 02:32:25 +00:00 · 2022-10-31 02:21:43 +00:00 · 2022-10-24 09:12:32 +08:00
4 changed files with 296 additions and 1 deletions
--- a/DCF-1.0.0-add-loongarch64-support.patch
+++ b/DCF-1.0.0-add-loongarch64-support.patch
@ -0,0 +1,95 @@
+From d9f173dc91f4544664443a8302e3eb42fb88fba8 Mon Sep 17 00:00:00 2001
+From: Jingyun Hua <huajingyun@loongson.cn>
+Date: Mon, 29 May 2023 02:16:31 +0000
+Subject: [PATCH] DCF-1.0.0:add loongarch64 support
+
+---
+ CMakeLists.txt                          | 4 ++--
+ src/common/cm_concurrency/cm_spinlock.h | 5 +++++
+ src/common/cm_concurrency/cm_thread.c   | 2 ++
+ src/common/cm_utils/cm_checksum.h       | 2 +-
+ src/common/cm_utils/cm_memory.h         | 6 ++++++
+ 5 files changed, 16 insertions(+), 3 deletions(-)
+
+diff --git a/CMakeLists.txt b/CMakeLists.txt
+index 81d310b..c8ba6b5 100644
+--- a/CMakeLists.txt
+++ b/CMakeLists.txt
+@@ -89,7 +89,7 @@ if (UNIX)
+ 
+         add_compile_options(-mtune=cortex-a72 -fsigned-char -g -ggdb3 -march=armv8-a+crc -funwind-tables)
+     else ()
+-        add_compile_options(-msse4.2 )
+        add_compile_options()
+     endif ()
+     Add_Definitions(-DWSEC_COMPILE_CAC_OPENSSL -DWSEC_AES_GCM_SUPPORT -DWSEC_USE_OPENSSL_110)
+ else ()
+@@ -106,4 +106,4 @@ add_subdirectory(src)
+ OPTION(TEST "option for test module" ON)
+ if (TEST)
+     add_subdirectory(test)
+-endif()
+\ No newline at end of file
+endif()
+diff --git a/src/common/cm_concurrency/cm_spinlock.h b/src/common/cm_concurrency/cm_spinlock.h
+index 7965853..3b6d961 100644
+--- a/src/common/cm_concurrency/cm_spinlock.h
+++ b/src/common/cm_concurrency/cm_spinlock.h
+@@ -68,6 +68,11 @@ typedef struct st_spin_statis {
+     {                            \
+         __asm__ volatile("nop"); \
+     }
+#elif defined(__loongarch64)
+#define fas_cpu_pause() \
+	{			   \
+        __asm__ volatile("dbar 0"); \
+	}
+ #else
+ #define fas_cpu_pause()            \
+     {                              \
+diff --git a/src/common/cm_concurrency/cm_thread.c b/src/common/cm_concurrency/cm_thread.c
+index 2d0aa2a..0bbf502 100644
+--- a/src/common/cm_concurrency/cm_thread.c
+++ b/src/common/cm_concurrency/cm_thread.c
+@@ -296,6 +296,8 @@ uint32 cm_get_current_thread_id()
+ #define __SYS_GET_SPID 186
+ #elif (defined __aarch64__)
+ #define __SYS_GET_SPID 178
+#elif (defined __loongarch64)
+#define __SYS_GET_SPID 178
+ #endif
+ #define gettid() syscall(__SYS_GET_SPID)
+ 
+diff --git a/src/common/cm_utils/cm_checksum.h b/src/common/cm_utils/cm_checksum.h
+index 85bb9fa..3d8bd8f 100644
+--- a/src/common/cm_utils/cm_checksum.h
+++ b/src/common/cm_utils/cm_checksum.h
+@@ -26,7 +26,7 @@
+ 
+ #include "cm_defs.h"
+ 
+-#if defined(__arm__) || defined(__aarch64__)
+#if defined(__arm__) || defined(__aarch64__) || defined(__loongarch64)
+ #ifdef __has_include
+ #if __has_include(<arm_acle.h>)
+ #include <arm_acle.h>
+diff --git a/src/common/cm_utils/cm_memory.h b/src/common/cm_utils/cm_memory.h
+index 988b78e..4a1debf 100644
+--- a/src/common/cm_utils/cm_memory.h
+++ b/src/common/cm_utils/cm_memory.h
+@@ -56,6 +56,12 @@ extern "C" {
+         __asm__ volatile("dmb ish" ::     \
+                              : "memory"); \
+     }
+#elif defined(__loongarch64)
+#define CM_MFENCE \
+	{				\
+        __asm__ volatile("dbar 0" ::     \
+                             : "memory"); \
+	}
+ #else
+ #define CM_MFENCE                         \
+     {                                     \
+-- 
+2.33.0
+
--- a/DCF-1.0.0-add-riscv64-support.patch
+++ b/DCF-1.0.0-add-riscv64-support.patch
@ -0,0 +1,85 @@
+From 645a5d63a1cbf866babdce9eade8d5719f62a7fc Mon Sep 17 00:00:00 2001
+From: misaka00251 <liuxin@iscas.ac.cn>
+Date: Fri, 28 Jul 2023 15:19:20 +0800
+Subject: [PATCH] Add riscv64 support
+
+---
+ CMakeLists.txt                          | 2 +-
+ src/common/cm_concurrency/cm_spinlock.h | 2 +-
+ src/common/cm_concurrency/cm_thread.c   | 2 +-
+ src/common/cm_utils/cm_checksum.h       | 2 +-
+ src/common/cm_utils/cm_memory.h         | 6 ++++++
+ 5 files changed, 10 insertions(+), 4 deletions(-)
+
+diff --git a/CMakeLists.txt b/CMakeLists.txt
+index 0380198..89d8551 100644
+--- a/CMakeLists.txt
+++ b/CMakeLists.txt
+@@ -89,7 +89,7 @@ if (UNIX)
+ 
+         add_compile_options(-mtune=cortex-a72 -fsigned-char -g -ggdb3 -march=armv8-a+crc -funwind-tables)
+     else ()
+-        add_compile_options(-msse4.2 )
+        add_compile_options()
+     endif ()
+     Add_Definitions(-DWSEC_COMPILE_CAC_OPENSSL -DWSEC_AES_GCM_SUPPORT -DWSEC_USE_OPENSSL_110)
+ else ()
+diff --git a/src/common/cm_concurrency/cm_spinlock.h b/src/common/cm_concurrency/cm_spinlock.h
+index 7965853..c7ef986 100644
+--- a/src/common/cm_concurrency/cm_spinlock.h
+++ b/src/common/cm_concurrency/cm_spinlock.h
+@@ -37,7 +37,7 @@ extern "C" {
+ 
+ typedef volatile uint32 spinlock_t;
+ typedef volatile uint32 ip_spinlock_t;
+-#if defined(__arm__) || defined(__aarch64__)
+#if defined(__arm__) || defined(__aarch64__) || defined(_riscv)
+ #define GS_INIT_SPIN_LOCK(lock)                       \
+     {                                                 \
+         __atomic_store_n(&lock, 0, __ATOMIC_SEQ_CST); \
+diff --git a/src/common/cm_concurrency/cm_thread.c b/src/common/cm_concurrency/cm_thread.c
+index 2d0aa2a..fd5f0f1 100644
+--- a/src/common/cm_concurrency/cm_thread.c
+++ b/src/common/cm_concurrency/cm_thread.c
+@@ -294,7 +294,7 @@ uint32 cm_get_current_thread_id()
+ {
+ #if (defined __x86_64__)
+ #define __SYS_GET_SPID 186
+-#elif (defined __aarch64__)
+#elif (defined __aarch64__) || defined(__riscv)
+ #define __SYS_GET_SPID 178
+ #endif
+ #define gettid() syscall(__SYS_GET_SPID)
+diff --git a/src/common/cm_utils/cm_checksum.h b/src/common/cm_utils/cm_checksum.h
+index 85bb9fa..06e60ca 100644
+--- a/src/common/cm_utils/cm_checksum.h
+++ b/src/common/cm_utils/cm_checksum.h
+@@ -26,7 +26,7 @@
+ 
+ #include "cm_defs.h"
+ 
+-#if defined(__arm__) || defined(__aarch64__)
+#if defined(__arm__) || defined(__aarch64__) || defined(__riscv)
+ #ifdef __has_include
+ #if __has_include(<arm_acle.h>)
+ #include <arm_acle.h>
+diff --git a/src/common/cm_utils/cm_memory.h b/src/common/cm_utils/cm_memory.h
+index 988b78e..05520a6 100644
+--- a/src/common/cm_utils/cm_memory.h
+++ b/src/common/cm_utils/cm_memory.h
+@@ -56,6 +56,12 @@ extern "C" {
+         __asm__ volatile("dmb ish" ::     \
+                              : "memory"); \
+     }
+#elif defined(__riscv)
+#define CM_MFENCE                         \
+    {                                     \
+        __asm__ volatile("fence " iorw "," iorw :: \
+                             : "memory"); \
+    }
+ #else
+ #define CM_MFENCE                         \
+     {                                     \
+-- 
+2.39.2 (Apple Git-143)
+
--- a/DCF-1.0.0-sw.patch
+++ b/DCF-1.0.0-sw.patch
@ -0,0 +1,76 @@
+diff -Nuar DCF-1.0.0.org/CMakeLists.txt DCF-1.0.0.sw/CMakeLists.txt
+--- DCF-1.0.0.org/CMakeLists.txt	2022-06-13 11:22:02.120000000 +0000
+++ DCF-1.0.0.sw/CMakeLists.txt	2022-06-13 11:22:51.510000000 +0000
+@@ -89,7 +89,7 @@
+ 
+         add_compile_options(-mtune=cortex-a72 -fsigned-char -g -ggdb3 -march=armv8-a+crc -funwind-tables)
+     else ()
+-        add_compile_options(-msse4.2 )
+        add_compile_options( )
+     endif ()
+     Add_Definitions(-DWSEC_COMPILE_CAC_OPENSSL -DWSEC_AES_GCM_SUPPORT -DWSEC_USE_OPENSSL_110)
+ else ()
+@@ -106,4 +106,4 @@
+ OPTION(TEST "option for test module" ON)
+ if (TEST)
+     add_subdirectory(test)
+-endif()
+\ No newline at end of file
+endif()
+diff -Nuar DCF-1.0.0.org/src/common/cm_concurrency/cm_spinlock.h DCF-1.0.0.sw/src/common/cm_concurrency/cm_spinlock.h
+--- DCF-1.0.0.org/src/common/cm_concurrency/cm_spinlock.h	2022-06-13 11:22:02.090000000 +0000
+++ DCF-1.0.0.sw/src/common/cm_concurrency/cm_spinlock.h	2022-06-13 16:12:03.530000000 +0000
+@@ -68,6 +68,9 @@
+     {                            \
+         __asm__ volatile("nop"); \
+     }
+#elif defined(__sw_64__)
+#define fas_cpu_pause() \
+	{}
+ #else
+ #define fas_cpu_pause()            \
+     {                              \
+diff -Nuar DCF-1.0.0.org/src/common/cm_concurrency/cm_thread.c DCF-1.0.0.sw/src/common/cm_concurrency/cm_thread.c
+--- DCF-1.0.0.org/src/common/cm_concurrency/cm_thread.c	2022-06-13 11:22:02.100000000 +0000
+++ DCF-1.0.0.sw/src/common/cm_concurrency/cm_thread.c	2022-06-13 16:39:23.220000000 +0000
+@@ -296,6 +296,8 @@
+ #define __SYS_GET_SPID 186
+ #elif (defined __aarch64__)
+ #define __SYS_GET_SPID 178
+#elif (defined __sw_64__)
+#define __SYS_GET_SPID 378
+ #endif
+ #define gettid() syscall(__SYS_GET_SPID)
+ 
+diff -Nuar DCF-1.0.0.org/src/common/cm_utils/cm_checksum.h DCF-1.0.0.sw/src/common/cm_utils/cm_checksum.h
+--- DCF-1.0.0.org/src/common/cm_utils/cm_checksum.h	2022-06-13 11:22:02.100000000 +0000
+++ DCF-1.0.0.sw/src/common/cm_utils/cm_checksum.h	2022-06-13 16:33:54.130000000 +0000
+@@ -26,7 +26,7 @@
+ 
+ #include "cm_defs.h"
+ 
+-#if defined(__arm__) || defined(__aarch64__)
+#if defined(__arm__) || defined(__aarch64__) || defined(__sw_64__)
+ #ifdef __has_include
+ #if __has_include(<arm_acle.h>)
+ #include <arm_acle.h>
+diff -Nuar DCF-1.0.0.org/src/common/cm_utils/cm_memory.h DCF-1.0.0.sw/src/common/cm_utils/cm_memory.h
+--- DCF-1.0.0.org/src/common/cm_utils/cm_memory.h	2022-06-13 11:22:02.100000000 +0000
+++ DCF-1.0.0.sw/src/common/cm_utils/cm_memory.h	2022-06-13 16:10:02.430000000 +0000
+@@ -50,12 +50,15 @@
+         __asm {mfence }  \
+     }
+ #endif
+-#elif defined(__arm__) || defined(__aarch64__)
+#elif defined(__arm__) || defined(__aarch64__) 
+ #define CM_MFENCE                         \
+     {                                     \
+         __asm__ volatile("dmb ish" ::     \
+                              : "memory"); \
+     }
+#elif defined(__sw_64__)
+#define CM_MFENCE \
+	{}	
+ #else
+ #define CM_MFENCE                         \
+     {                                     \
--- a/opengauss-dcf.spec
+++ b/opengauss-dcf.spec
@ -1,12 +1,15 @@
 Name:             DCF
 Version:          1.0.0
-Release:          1
+Release:          6
 Summary:          A distributed consensus framework library
 License:          MulanPSL-2.0
 URL:              https://gitee.com/opengauss/DCF
 Source0:          %{name}-%{version}.tar.gz

 Patch1:           01-boundcheck.patch
+Patch2:           DCF-1.0.0-sw.patch
+Patch3:           DCF-1.0.0-add-loongarch64-support.patch
+Patch4:           DCF-1.0.0-add-riscv64-support.patch

 BuildRequires: cmake gcc gcc-c++ lz4-devel openssl-devel zstd-devel libboundscheck cjson-devel

@ -18,6 +21,15 @@ DCF is A distributed consensus framework library for openGauss
 %prep
 %setup -q
 %patch1 -p1
+%ifarch sw_64
+%patch2 -p1
+%endif
+%ifarch loongarch64
+%patch3 -p1
+%endif
+%ifarch riscv64
+%patch4 -p1
+%endif

 %build
 cmake -DCMAKE_BUILD_TYPE=Release -DUSE32BIT=OFF -DTEST=OFF -DENABLE_EXPORT_API=OFF CMakeLists.txt
@ -26,9 +38,17 @@ cmake -DCMAKE_BUILD_TYPE=Release -DUSE32BIT=OFF -DTEST=OFF -DENABLE_EXPORT_API=O

 %install
 mkdir -p %{buildroot}/%{_prefix}/include
+%ifarch sw_64
 mkdir -p %{buildroot}/%{_prefix}/lib
+%else
+mkdir -p %{buildroot}/%{_prefix}/lib64
+%endif
 cp src/interface/dcf_interface.h %{buildroot}/%{_prefix}/include
+%ifarch sw_64
 cp output/lib/libdcf.* %{buildroot}/%{_prefix}/lib
+%else
+cp output/lib/libdcf.* %{buildroot}/%{_prefix}/lib64
+%endif

 %post

@ -37,8 +57,27 @@ cp output/lib/libdcf.* %{buildroot}/%{_prefix}/lib
 %files
 %defattr (-,root,root)
 %{_prefix}/include/dcf_interface.h
+%ifarch sw_64
 %{_prefix}/lib/libdcf.so
+%else
+%{_prefix}/lib64/libdcf.so
+%endif

 %changelog
+* Fri Jul 28 2023 misaka00251 <liuxin@iscas.ac.cn> - 1.0.0-6
+- Add riscv64 support
+
+* Mon May 29 2023 huajingyun<huajingyun@loongson.cn> - 1.0.0-5
+- add loongarch64 support
+
+* Mon Oct 24 2022 wuzx<wuzx1226@qq.com> - 1.0.0-4
+- change lib64 to lib when in sw64 architecture
+
+* Thu Jul 28 2022 wuzx<wuzx1226@qq.com> - 1.0.0-3
+- add sw64 patch
+
+* Thu Feb 10 2022 zhangxubo <zhangxubo1@huawei.com> - 1.0.0-2
+- #I4T3R3 move library file to /usr/lib64 path.
+
 * Wed Dec 1 2021 zhangxubo <zhangxubo1@huawei.com> - 1.0.0-1
 - Package init
Author	SHA1	Message	Date
openeuler-ci-bot	89c3e2ea58	!15 Add riscv64 support From: @misaka00251 Reviewed-by: @dillon_chen Signed-off-by: @dillon_chen	2023-08-25 10:23:13 +00:00
misaka00251	af3815555e	Add riscv64 support	2023-07-28 15:19:37 +08:00
openeuler-ci-bot	cfbee4de3e	!12 add loongarch64 support From: @huajingyun Reviewed-by: @dillon_chen Signed-off-by: @dillon_chen	2023-05-31 09:54:56 +00:00
Jingyun Hua	0ade41de6e	add loongarch64 support	2023-05-29 02:32:25 +00:00
openeuler-ci-bot	89bbb764a2	!9 change lib64 to lib when in sw64 architecture From: @wuzx065891 Reviewed-by: @dillon_chen Signed-off-by: @dillon_chen	2022-10-31 02:21:43 +00:00
wzx	803bab67a3	change lib64 to lib when in sw64 architecture Signed-off-by: wzx <wuzx1226@qq.com>	2022-10-24 09:12:32 +08:00
openeuler-ci-bot	83900bf696	!6 添加sw架构 From: @wuzx065891 Reviewed-by: @dillon_chen Signed-off-by: @dillon_chen	2022-09-14 01:46:56 +00:00
wzx	c9b4d7b29d	sw	2022-08-02 16:42:19 +08:00
wzx	e2ff5ebc06	sw	2022-08-02 16:17:47 +08:00
openeuler-ci-bot	fbe5c95f40	!3 move libdcf library file to lib64 path From: @zhang_xubo Reviewed-by: @bzhaoop Signed-off-by: @bzhaoop	2022-02-10 08:32:12 +00:00
zhang_xubo	38537cfaf9	move libdcf library file to lib64 path	2022-02-10 11:40:14 +08:00