!68 winsys/radeon: pass priv instead NULL to radeon_bo_can_reclaim

From: @Venland 
Reviewed-by: @weidongkl 
Signed-off-by: @weidongkl

0001-evergreen-big-endian.patch

@@ -1,26 +0,0 @@
-From 0ec3bdb2264b491fd3f5dc4e638b4c12611ef219 Mon Sep 17 00:00:00 2001
-From: Igor Gnatenko <i.gnatenko.brain@gmail.com>
-Date: Sun, 20 Mar 2016 13:27:45 +0100
-Subject: [PATCH 3/4] evergreen big endian
-
-Signed-off-by: Igor Gnatenko <i.gnatenko.brain@gmail.com>
----
- src/gallium/drivers/r600/r600_state_common.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c
-index cac240e..4b620a1 100644
---- a/src/gallium/drivers/r600/r600_state_common.c
-+++ b/src/gallium/drivers/r600/r600_state_common.c
-@@ -2716,7 +2716,7 @@ uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format forma
- 
- uint32_t r600_colorformat_endian_swap(uint32_t colorformat, bool do_endian_swap)
- {
--	if (R600_BIG_ENDIAN) {
-+	if (0 && R600_BIG_ENDIAN) {
- 		switch(colorformat) {
- 		/* 8-bit buffers. */
- 		case V_0280A0_COLOR_4_4:
--- 
-2.7.4
-

0001-llvmpipe-add-loongarch64-basic-support.patch

@@ -0,0 +1,134 @@
+From 7e21e1bfc1e9cf8031c55df2cc1f334deedce159 Mon Sep 17 00:00:00 2001
+From: zhaojiale <zhaojiale@loongson.cn>
+Date: Thu, 7 Dec 2023 06:21:08 +0800
+Subject: [PATCH 1/2] llvmpipe: add loongarch64 basic support
+
+Signed-off-by: zhaojiale <zhaojiale@loongson.cn>
+---
+ .../auxiliary/gallivm/lp_bld_debug.cpp        |  6 ++++++
+ src/gallium/auxiliary/gallivm/lp_bld_debug.h  |  6 ++++++
+ src/gallium/auxiliary/gallivm/lp_bld_init.c   | 20 +++++++++++++++++--
+ src/util/detect_arch.h                        | 14 +++++++++++++
+ 5 files changed, 48 insertions(+), 2 deletions(-)
+
+diff --git a/src/gallium/auxiliary/gallivm/lp_bld_debug.cpp b/src/gallium/auxiliary/gallivm/lp_bld_debug.cpp
+index 2918d38..eeed17d 100644
+--- a/src/gallium/auxiliary/gallivm/lp_bld_debug.cpp
++++ b/src/gallium/auxiliary/gallivm/lp_bld_debug.cpp
+@@ -171,6 +171,12 @@ disassemble(const void* func, std::ostream &buffer)
+       }
+ #endif
+ 
++#if DETECT_ARCH_LOONGARCH64
++   if (Size == 4 && (*(uint32_t *)(bytes+pc) >> 26) == 0x13) {
++      break;
++   }
++#endif
++
+       /*
+        * Advance.
+        */
+diff --git a/src/gallium/auxiliary/gallivm/lp_bld_debug.h b/src/gallium/auxiliary/gallivm/lp_bld_debug.h
+index a8db59b..30100aa 100644
+--- a/src/gallium/auxiliary/gallivm/lp_bld_debug.h
++++ b/src/gallium/auxiliary/gallivm/lp_bld_debug.h
+@@ -49,6 +49,12 @@
+ #define GALLIVM_PERF_NO_OPT          (1 << 3)
+ #define GALLIVM_PERF_NO_AOS_SAMPLING (1 << 4)
+ 
++#if DETECT_ARCH_LOONGARCH64
++#define GALLIVM_PERF_OPT_O1        (1 << 5)
++#define GALLIVM_PERF_OPT_O2        (1 << 6)
++#define GALLIVM_PERF_OPT_O3        (1 << 7)
++#endif
++
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init.c b/src/gallium/auxiliary/gallivm/lp_bld_init.c
+index 9750cf7..3c67c11 100644
+--- a/src/gallium/auxiliary/gallivm/lp_bld_init.c
++++ b/src/gallium/auxiliary/gallivm/lp_bld_init.c
+@@ -50,7 +50,7 @@
+ #if LLVM_VERSION_MAJOR >= 7
+ #include <llvm-c/Transforms/Utils.h>
+ #endif
+-#if LLVM_VERSION_MAJOR <= 8 && (DETECT_ARCH_AARCH64 || DETECT_ARCH_ARM || DETECT_ARCH_S390 || DETECT_ARCH_MIPS64)
++#if LLVM_VERSION_MAJOR <= 8 && (DETECT_ARCH_AARCH64 || DETECT_ARCH_ARM || DETECT_ARCH_S390 || DETECT_ARCH_MIPS64 || DETECT_ARCH_LOONGARCH64)
+ #include <llvm-c/Transforms/IPO.h>
+ #endif
+ #include <llvm-c/Transforms/Coroutines.h>
+@@ -64,6 +64,11 @@ static const struct debug_named_value lp_bld_perf_flags[] = {
+    { "no_quad_lod", GALLIVM_PERF_NO_QUAD_LOD, "disable quad_lod optimization" },
+    { "no_aos_sampling", GALLIVM_PERF_NO_AOS_SAMPLING, "disable aos sampling optimization" },
+    { "nopt",   GALLIVM_PERF_NO_OPT, "disable optimization passes to speed up shader compilation" },
++#if DETECT_ARCH_LOONGARCH64
++   { "o3",   GALLIVM_PERF_OPT_O3, "enable aggressive optimization passes" },
++   { "o2",   GALLIVM_PERF_OPT_O2, "enable medium optimization passes" },
++   { "o1",   GALLIVM_PERF_OPT_O1, "enable less optimization passes" },
++#endif
+    DEBUG_NAMED_VALUE_END
+ };
+ 
+@@ -141,7 +146,7 @@ create_pass_manager(struct gallivm_state *gallivm)
+    }
+ 
+ #if GALLIVM_HAVE_CORO == 1
+-#if LLVM_VERSION_MAJOR <= 8 && (DETECT_ARCH_AARCH64 || DETECT_ARCH_ARM || DETECT_ARCH_S390 || DETECT_ARCH_MIPS64)
++#if LLVM_VERSION_MAJOR <= 8 && (DETECT_ARCH_AARCH64 || DETECT_ARCH_ARM || DETECT_ARCH_S390 || DETECT_ARCH_MIPS64 || DETECT_ARCH_LOONGARCH64)
+    LLVMAddArgumentPromotionPass(gallivm->cgpassmgr);
+    LLVMAddFunctionAttrsPass(gallivm->cgpassmgr);
+ #endif
+@@ -281,6 +286,17 @@ init_gallivm_engine(struct gallivm_state *gallivm)
+          optlevel = Default;
+       }
+ 
++#if DETECT_ARCH_LOONGARCH64
++      if (gallivm_perf & GALLIVM_PERF_OPT_O3)
++         optlevel = Aggressive;
++      else if (gallivm_perf & GALLIVM_PERF_OPT_O2)
++         optlevel = Default;
++      else if (gallivm_perf & GALLIVM_PERF_OPT_O1)
++         optlevel = Less;
++      else
++         optlevel = Default;
++#endif
++
+       ret = lp_build_create_jit_compiler_for_module(&gallivm->engine,
+                                                     &gallivm->code,
+                                                     gallivm->cache,
+diff --git a/src/util/detect_arch.h b/src/util/detect_arch.h
+index 75fa7ed..c0f8cdb 100644
+--- a/src/util/detect_arch.h
++++ b/src/util/detect_arch.h
+@@ -97,6 +97,12 @@
+ #define DETECT_ARCH_HPPA 1
+ #endif
+ 
++#if defined(__loongarch_lp64) || defined(__loongarch64)
++#define DETECT_ARCH_LOONGARCH64 1
++#elif defined(__loongarch__)
++#define DETECT_ARCH_LOONGARCH 1
++#endif
++
+ #if defined(__riscv)
+ #define DETECT_ARCH_RISCV 1
+ #if __riscv_xlen == 64
+@@ -148,6 +154,14 @@
+ #define DETECT_ARCH_HPPA 0
+ #endif
+ 
++#ifndef DETECT_ARCH_LOONGARCH
++#define DETECT_ARCH_LOONGARCH 0
++#endif
++
++#ifndef DETECT_ARCH_LOONGARCH64
++#define DETECT_ARCH_LOONGARCH64 0
++#endif
++
+ #ifndef DETECT_ARCH_RISCV
+ #define DETECT_ARCH_RISCV 0
+ #endif
+-- 
+2.43.0
+

0002-llvmpipe-support-loongarch64-orcjit.patch

@@ -0,0 +1,35 @@
+From 486ff712babd672bdaa8830e250653f12879f1da Mon Sep 17 00:00:00 2001
+From: zhaojiale <zhaojiale@loongson.cn>
+Date: Sun, 12 May 2024 00:17:10 +0800
+Subject: [PATCH 2/2] llvmpipe: support loongarch64 orcjit
+
+Signed-off-by: zhaojiale <zhaojiale@loongson.cn>
+---
+ src/gallium/auxiliary/gallivm/lp_bld_init_orc.cpp | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init_orc.cpp b/src/gallium/auxiliary/gallivm/lp_bld_init_orc.cpp
+index 797c9e1..17767f4 100644
+--- a/src/gallium/auxiliary/gallivm/lp_bld_init_orc.cpp
++++ b/src/gallium/auxiliary/gallivm/lp_bld_init_orc.cpp
+@@ -52,7 +52,7 @@
+ /* conflict with ObjectLinkingLayer.h */
+ #include "util/u_memory.h"
+ 
+-#if DETECT_ARCH_RISCV64 == 1 || DETECT_ARCH_RISCV32 == 1 || (defined(_WIN32) && LLVM_VERSION_MAJOR >= 15)
++#if DETECT_ARCH_RISCV64 == 1 || DETECT_ARCH_RISCV32 == 1 || DETECT_ARCH_LOONGARCH64 == 1 || (defined(_WIN32) && LLVM_VERSION_MAJOR >= 15)
+ /* use ObjectLinkingLayer (JITLINK backend) */
+ #define USE_JITLINK
+ #endif
+@@ -570,7 +570,7 @@ llvm::orc::JITTargetMachineBuilder LPJit::create_jtdb() {
+ 
+    std::vector<std::string> MAttrs;
+ 
+-#if LLVM_VERSION_MAJOR >= 4 && (DETECT_ARCH_X86 == 1 || DETECT_ARCH_X86_64 == 1 || DETECT_ARCH_ARM == 1)
++#if LLVM_VERSION_MAJOR >= 4 && (DETECT_ARCH_X86 == 1 || DETECT_ARCH_X86_64 == 1 || DETECT_ARCH_ARM == 1 || DETECT_ARCH_LOONGARCH64 == 1)
+    /* llvm-3.3+ implements sys::getHostCPUFeatures for Arm
+     * and llvm-3.7+ for x86, which allows us to enable/disable
+     * code generation based on the results of cpuid on these
+-- 
+2.43.0
+

backport-pass-priv-instead-NULL-to-radeon_bo_can_reclaim.patch

@@ -0,0 +1,35 @@
+From 99017891cad55972c26c0ca8354f48e722b37a66 Mon Sep 17 00:00:00 2001
+From: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
+Date: Mon, 18 Mar 2024 11:52:50 +0100
+Subject: [PATCH] winsys/radeon: pass priv instead NULL to
+ radeon_bo_can_reclaim
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This fixes a NULL pointer issue.
+
+Fixes: 4a078e693e9 ("r300,r600,radeon/winsys: always pass the winsys to radeon_bo_reference")
+Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10613
+Reviewed-by: Marek Ol拧谩k <marek.olsak@amd.com>
+Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28240>
+---
+ src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+index 2e1d9c488e2ca..7979cad75fac4 100644
+--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
++++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+@@ -729,7 +729,7 @@ bool radeon_bo_can_reclaim_slab(void *priv, struct pb_slab_entry *entry)
+ {
+    struct radeon_bo *bo = container_of(entry, struct radeon_bo, u.slab.entry);
+ 
+-   return radeon_bo_can_reclaim(NULL, &bo->base);
++   return radeon_bo_can_reclaim(priv, &bo->base);
+ }
+ 
+ static void radeon_bo_slab_destroy(void *winsys, struct pb_buffer_lean *_buf)
+-- 
+GitLab
+

llvmpipe-add-riscv-support-in-orcjit.patch

@@ -1,136 +0,0 @@
-From 337f91f990070b6a3251550c682fec5ffcce478c Mon Sep 17 00:00:00 2001
-From: Alex Fan <alex.fan.q@gmail.com>
-Date: Fri, 29 Jul 2022 12:44:14 +1000
-Subject: [PATCH] llvmpipe: add riscv support in orcjit
-
-assume cpu supports extension +i,+m,+a,+f,+d,+c
----
- .../auxiliary/gallivm/lp_bld_init_orc.cpp     | 58 ++++++++++++++++++-
- src/util/detect_arch.h                        | 16 +++++
- 2 files changed, 73 insertions(+), 1 deletion(-)
-
-diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init_orc.cpp b/src/gallium/auxiliary/gallivm/lp_bld_init_orc.cpp
-index b245edc5586..eaacebd65d6 100644
---- a/src/gallium/auxiliary/gallivm/lp_bld_init_orc.cpp
-+++ b/src/gallium/auxiliary/gallivm/lp_bld_init_orc.cpp
-@@ -48,7 +48,7 @@
- /* conflict with ObjectLinkingLayer.h */
- #include "util/u_memory.h"
- 
--#if (defined(_WIN32) && LLVM_VERSION_MAJOR >= 15)
-+#if DETECT_ARCH_RISCV64 || DETECT_ARCH_RISCV32 || (defined(_WIN32) && LLVM_VERSION_MAJOR >= 15)
- /* use ObjectLinkingLayer (JITLINK backend) */
- #define USE_JITLINK
- #endif
-@@ -521,6 +521,30 @@ llvm::orc::JITTargetMachineBuilder LPJit::create_jtdb() {
-    options.StackAlignmentOverride = 4;
- #endif
- 
-+#if DETECT_ARCH_RISCV64
-+#if defined(__riscv_float_abi_soft)
-+   options.MCOptions.ABIName = "lp64";
-+#elif defined(__riscv_float_abi_single)
-+   options.MCOptions.ABIName = "lp64f";
-+#elif defined(__riscv_float_abi_double)
-+   options.MCOptions.ABIName = "lp64d";
-+#else
-+#error "GALLIVM: unknown target riscv float abi"
-+#endif
-+#endif
-+
-+#if DETECT_ARCH_RISCV32
-+#if defined(__riscv_float_abi_soft)
-+   options.MCOptions.ABIName = "ilp32";
-+#elif defined(__riscv_float_abi_single)
-+   options.MCOptions.ABIName = "ilp32f";
-+#elif defined(__riscv_float_abi_double)
-+   options.MCOptions.ABIName = "ilp32d";
-+#else
-+#error "GALLIVM: unknown target riscv float abi"
-+#endif
-+#endif
-+
-    JTMB.setOptions(options);
- 
-    std::vector<std::string> MAttrs;
-@@ -619,6 +643,14 @@ llvm::orc::JITTargetMachineBuilder LPJit::create_jtdb() {
-    MAttrs.push_back("+fp64");
- #endif
- 
-+#if DETECT_ARCH_RISCV64
-+   /* Before riscv is more matured and util_get_cpu_caps() is implemented,
-+    * assume this for now since most of linux capable riscv machine are
-+    * riscv64gc
-+    */
-+   MAttrs = {"+m","+c","+a","+d","+f"};
-+#endif
-+
-    JTMB.addFeatures(MAttrs);
- 
-    if (gallivm_debug & (GALLIVM_DEBUG_IR | GALLIVM_DEBUG_ASM | GALLIVM_DEBUG_DUMP_BC)) {
-@@ -686,6 +718,30 @@ llvm::orc::JITTargetMachineBuilder LPJit::create_jtdb() {
-       MCPU = util_get_cpu_caps()->has_msa ? "mips64r5" : "mips64r2";
- #endif
- 
-+#if DETECT_ARCH_RISCV64
-+   /**
-+    * should be fixed with https://reviews.llvm.org/D121149 in llvm 15,
-+    * set it anyway for llvm 14
-+    */
-+   if (MCPU == "generic")
-+      MCPU = "generic-rv64";
-+
-+   JTMB.setCodeModel(CodeModel::Medium);
-+   JTMB.setRelocationModel(Reloc::PIC_);
-+#endif
-+
-+#if DETECT_ARCH_RISCV32
-+   /**
-+    * should be fixed with https://reviews.llvm.org/D121149 in llvm 15,
-+    * set it anyway for llvm 14
-+    */
-+   if (MCPU == "generic")
-+      MCPU = "generic-rv32";
-+
-+   JTMB.setCodeModel(CodeModel::Medium);
-+   JTMB.setRelocationModel(Reloc::PIC_);
-+#endif
-+
-    JTMB.setCPU(MCPU);
-    if (gallivm_debug & (GALLIVM_DEBUG_IR | GALLIVM_DEBUG_ASM | GALLIVM_DEBUG_DUMP_BC)) {
-       debug_printf("llc -mcpu option: %s\n", MCPU.c_str());
-diff --git a/src/util/detect_arch.h b/src/util/detect_arch.h
-index 334358fcc26..34c0928216d 100644
---- a/src/util/detect_arch.h
-+++ b/src/util/detect_arch.h
-@@ -97,6 +97,14 @@
- #define DETECT_ARCH_MIPS 1
- #endif
- 
-+#if defined(__riscv)
-+#if __riscv_xlen == 64
-+#define DETECT_ARCH_RISCV64 1
-+#elif __riscv_xlen == 32
-+#define DETECT_ARCH_RISCV32 1
-+#endif
-+#endif
-+
- #ifndef DETECT_ARCH_X86
- #define DETECT_ARCH_X86 0
- #endif
-@@ -137,4 +145,12 @@
- #define DETECT_ARCH_MIPS 0
- #endif
- 
-+#ifndef DETECT_ARCH_RISCV32
-+#define DETECT_ARCH_RISCV32 0
-+#endif
-+
-+#ifndef DETECT_ARCH_RISCV64
-+#define DETECT_ARCH_RISCV64 0
-+#endif
-+
- #endif /* UTIL_DETECT_ARCH_H_ */
--- 
-2.41.0
-

llvmpipe-make-unnamed-global-have-internal-linkage.patch

@@ -1,29 +0,0 @@
-From 3148f08bd0207a8bd50ff5c8b82d7a5b0871c3d1 Mon Sep 17 00:00:00 2001
-From: Alex Fan <alex.fan.q@gmail.com>
-Date: Mon, 28 Nov 2022 22:29:44 +1100
-Subject: [PATCH] llvmpipe: make unnamed global have internal linkage
-
-work around bug https://github.com/llvm/llvm-project/issues/54813
-Being unnamed makes it not useable from other module, therefore
-changing to internal linkage is safe
-
-Signed-off-by: Alex Fan <alex.fan.q@gmail.com>
----
- src/gallium/drivers/llvmpipe/lp_state_fs.c | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/src/gallium/drivers/llvmpipe/lp_state_fs.c b/src/gallium/drivers/llvmpipe/lp_state_fs.c
-index 2a5977134b0..5a396b44137 100644
---- a/src/gallium/drivers/llvmpipe/lp_state_fs.c
-+++ b/src/gallium/drivers/llvmpipe/lp_state_fs.c
-@@ -3306,6 +3306,7 @@ generate_fragment(struct llvmpipe_context *lp,
-       LLVMValueRef glob_sample_pos =
-          LLVMAddGlobal(gallivm->module,
-                        LLVMArrayType(flt_type, key->coverage_samples * 2), "");
-+      LLVMSetLinkage(glob_sample_pos, LLVMInternalLinkage);
-       LLVMValueRef sample_pos_array;
- 
-       if (key->multisample && key->coverage_samples == 4) {
--- 
-2.41.0
-

mesa.spec

@@ -51,18 +51,19 @@
 
 Name:           mesa
 Summary:        Mesa graphics libraries
-Version:        23.1.6
-Release:        1
+Version:        24.0.3
+Release:        3
 
 License:        MIT
 URL:            http://www.mesa3d.org
-Source0:        https://mesa.freedesktop.org/archive/%{name}-%{version}.tar.xz
+Source0:        https://archive.mesa3d.org/%{name}-%{version}.tar.xz
 
 Patch1:         backport-fix-build-err-on-arm.patch
-Patch2:         0001-evergreen-big-endian.patch
-Patch3:         llvmpipe-add-an-implementation-with-llvm-orcjit.patch
-Patch4:         llvmpipe-add-riscv-support-in-orcjit.patch
-Patch5:         llvmpipe-make-unnamed-global-have-internal-linkage.patch
+Patch2:         0001-changed_by_upstream_26018_orcjit_patch.patch
+Patch3:         0001-llvmpipe-add-loongarch64-basic-support.patch
+Patch4:         0002-llvmpipe-support-loongarch64-orcjit.patch
+# https://gitlab.freedesktop.org/mesa/mesa/-/commit/99017891cad55972c26c0ca8354f48e722b37a66
+Patch5:         backport-pass-priv-instead-NULL-to-radeon_bo_can_reclaim.patch
 
 BuildRequires:  gcc
 BuildRequires:  gcc-c++
@@ -341,6 +342,7 @@ export ASFLAGS="--generate-missing-build-notes=yes"
   -Dglx=dri \
   -Degl=enabled \
   -Dglvnd=true \
+  -Dllvm-orcjit=true \
   -Dmicrosoft-clc=disabled \
   -Dllvm=enabled \
   -Dshared-llvm=enabled \
@@ -494,6 +496,7 @@ done
 %if 0%{?with_kmsro}
 %{_libdir}/dri/armada-drm_dri.so
 %{_libdir}/dri/exynos_dri.so
+%{_libdir}/dri/hdlcd_dri.so
 %{_libdir}/dri/hx8357d_dri.so
 %{_libdir}/dri/ili9225_dri.so
 %{_libdir}/dri/ili9341_dri.so
@@ -534,6 +537,14 @@ done
 %{_libdir}/dri/kms_swrast_dri.so
 %{_libdir}/dri/swrast_dri.so
 %{_libdir}/dri/virtio_gpu_dri.so
+%ifarch %{arm} aarch64
+%{_libdir}/dri/gm12u320_dri.so
+%{_libdir}/dri/ili9163_dri.so
+%{_libdir}/dri/ili9486_dri.so
+%{_libdir}/dri/panel-mipi-dbi_dri.so
+%{_libdir}/dri/sti_dri.so
+%{_libdir}/dri/udl_dri.so
+%endif
 
 %if %{with_hardware}
 %if 0%{?with_omx}
@@ -571,6 +582,22 @@ done
 %endif
 
 %changelog
+* Mon Dec 23 2024 liweigang <liweiganga@uniontech.com> - 24.0.3-3
+- sync upstream issue
+
+* Mon May 20 2024 zhaojiale <zhaojiale@loongson.cn> - 24.0.3-2
+- add upstream orcjit patch and support loongarch64 orcjit
+
+* Mon Mar 18 2024 liweigang <liweiganga@uniontech.com> - 24.0.3-1
+- update to version 24.0.3
+
+* Tue Dec 19 2023 zhangpan <zhangpan103@h-partners.com> - 23.3.1-1
+- upgrade to mesa-23.3.1
+
+* Thu Nov 02 2023 Jingwiw  <wangjingwei@iscas.ac.cn> - 23.2.1-1
+- upgrade to version 23.2.1
+- fix llvmpipe interface support for the new version
+
 * Sun Aug 20 2023 Funda Wang <fundawang@yeah.net> - 23.1.6-1
 - update to 23.1.6