upgrade to 23.2.1 and fix new interface

llvmpipe-add-riscv-support-in-orcjit.patch

@@ -1,32 +1,28 @@
-From 337f91f990070b6a3251550c682fec5ffcce478c Mon Sep 17 00:00:00 2001
+From b4cc97ac05b70fa328ad57cf6defee8113666cac Mon Sep 17 00:00:00 2001
 From: Alex Fan <alex.fan.q@gmail.com>
 Date: Fri, 29 Jul 2022 12:44:14 +1000
 Subject: [PATCH] llvmpipe: add riscv support in orcjit
 
 assume cpu supports extension +i,+m,+a,+f,+d,+c
 ---
- .../auxiliary/gallivm/lp_bld_init_orc.cpp     | 58 ++++++++++++++++++-
- src/util/detect_arch.h                        | 16 +++++
- 2 files changed, 73 insertions(+), 1 deletion(-)
-
 diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init_orc.cpp b/src/gallium/auxiliary/gallivm/lp_bld_init_orc.cpp
-index b245edc5586..eaacebd65d6 100644
+index 8ea4df7..91dde78 100644
 --- a/src/gallium/auxiliary/gallivm/lp_bld_init_orc.cpp
 +++ b/src/gallium/auxiliary/gallivm/lp_bld_init_orc.cpp
-@@ -48,7 +48,7 @@
+@@ -44,7 +44,7 @@
  /* conflict with ObjectLinkingLayer.h */
  #include "util/u_memory.h"
  
 -#if (defined(_WIN32) && LLVM_VERSION_MAJOR >= 15)
-+#if DETECT_ARCH_RISCV64 || DETECT_ARCH_RISCV32 || (defined(_WIN32) && LLVM_VERSION_MAJOR >= 15)
++#if defined(PIPE_ARCH_RISCV64) || defined(PIPE_ARCH_RISCV32) || (defined(_WIN32) && LLVM_VERSION_MAJOR >= 15)
  /* use ObjectLinkingLayer (JITLINK backend) */
  #define USE_JITLINK
  #endif
-@@ -521,6 +521,30 @@ llvm::orc::JITTargetMachineBuilder LPJit::create_jtdb() {
+@@ -551,6 +551,30 @@ llvm::orc::JITTargetMachineBuilder LPJit::create_jtdb() {
     options.StackAlignmentOverride = 4;
  #endif
  
-+#if DETECT_ARCH_RISCV64
++#if defined(PIPE_ARCH_RISCV64)
 +#if defined(__riscv_float_abi_soft)
 +   options.MCOptions.ABIName = "lp64";
 +#elif defined(__riscv_float_abi_single)
@@ -38,7 +34,7 @@ index b245edc5586..eaacebd65d6 100644
 +#endif
 +#endif
 +
-+#if DETECT_ARCH_RISCV32
++#if defined(PIPE_ARCH_RISCV32)
 +#if defined(__riscv_float_abi_soft)
 +   options.MCOptions.ABIName = "ilp32";
 +#elif defined(__riscv_float_abi_single)
@@ -53,11 +49,11 @@ index b245edc5586..eaacebd65d6 100644
     JTMB.setOptions(options);
  
     std::vector<std::string> MAttrs;
-@@ -619,6 +643,14 @@ llvm::orc::JITTargetMachineBuilder LPJit::create_jtdb() {
+@@ -649,6 +673,14 @@ llvm::orc::JITTargetMachineBuilder LPJit::create_jtdb() {
     MAttrs.push_back("+fp64");
  #endif
  
-+#if DETECT_ARCH_RISCV64
++#if defined(PIPE_ARCH_RISCV64)
 +   /* Before riscv is more matured and util_get_cpu_caps() is implemented,
 +    * assume this for now since most of linux capable riscv machine are
 +    * riscv64gc
@@ -67,12 +63,12 @@ index b245edc5586..eaacebd65d6 100644
 +
     JTMB.addFeatures(MAttrs);
  
-    if (gallivm_debug & (GALLIVM_DEBUG_IR | GALLIVM_DEBUG_ASM | GALLIVM_DEBUG_DUMP_BC)) {
-@@ -686,6 +718,30 @@ llvm::orc::JITTargetMachineBuilder LPJit::create_jtdb() {
+    if (::gallivm_debug & (GALLIVM_DEBUG_IR | GALLIVM_DEBUG_ASM | GALLIVM_DEBUG_DUMP_BC)) {
+@@ -716,6 +748,30 @@ llvm::orc::JITTargetMachineBuilder LPJit::create_jtdb() {
        MCPU = util_get_cpu_caps()->has_msa ? "mips64r5" : "mips64r2";
  #endif
  
-+#if DETECT_ARCH_RISCV64
++#if defined(PIPE_ARCH_RISCV64)
 +   /**
 +    * should be fixed with https://reviews.llvm.org/D121149 in llvm 15,
 +    * set it anyway for llvm 14
@@ -84,7 +80,7 @@ index b245edc5586..eaacebd65d6 100644
 +   JTMB.setRelocationModel(Reloc::PIC_);
 +#endif
 +
-+#if DETECT_ARCH_RISCV32
++#if defined(PIPE_ARCH_RISCV32)
 +   /**
 +    * should be fixed with https://reviews.llvm.org/D121149 in llvm 15,
 +    * set it anyway for llvm 14
@@ -100,37 +96,21 @@ index b245edc5586..eaacebd65d6 100644
     if (gallivm_debug & (GALLIVM_DEBUG_IR | GALLIVM_DEBUG_ASM | GALLIVM_DEBUG_DUMP_BC)) {
        debug_printf("llc -mcpu option: %s\n", MCPU.c_str());
 diff --git a/src/util/detect_arch.h b/src/util/detect_arch.h
-index 334358fcc26..34c0928216d 100644
+index 334358f..8c7bd15 100644
 --- a/src/util/detect_arch.h
 +++ b/src/util/detect_arch.h
-@@ -97,6 +97,14 @@
- #define DETECT_ARCH_MIPS 1
+@@ -137,4 +137,14 @@
+ #define DETECT_ARCH_MIPS 0
  #endif
  
 +#if defined(__riscv)
 +#if __riscv_xlen == 64
-+#define DETECT_ARCH_RISCV64 1
++#define PIPE_ARCH_RISCV64
 +#elif __riscv_xlen == 32
-+#define DETECT_ARCH_RISCV32 1
++#define PIPE_ARCH_RISCV32
++#else
++#error "pipe: unknown target riscv xlen"
 +#endif
 +#endif
-+
- #ifndef DETECT_ARCH_X86
- #define DETECT_ARCH_X86 0
- #endif
-@@ -137,4 +145,12 @@
- #define DETECT_ARCH_MIPS 0
- #endif
- 
-+#ifndef DETECT_ARCH_RISCV32
-+#define DETECT_ARCH_RISCV32 0
-+#endif
-+
-+#ifndef DETECT_ARCH_RISCV64
-+#define DETECT_ARCH_RISCV64 0
-+#endif
 +
  #endif /* UTIL_DETECT_ARCH_H_ */
--- 
-2.41.0
-

llvmpipe-make-unnamed-global-have-internal-linkage.patch

@@ -9,14 +9,11 @@ changing to internal linkage is safe
 
 Signed-off-by: Alex Fan <alex.fan.q@gmail.com>
 ---
- src/gallium/drivers/llvmpipe/lp_state_fs.c | 1 +
- 1 file changed, 1 insertion(+)
-
 diff --git a/src/gallium/drivers/llvmpipe/lp_state_fs.c b/src/gallium/drivers/llvmpipe/lp_state_fs.c
-index 2a5977134b0..5a396b44137 100644
+index 4e0b693..5b29610 100644
 --- a/src/gallium/drivers/llvmpipe/lp_state_fs.c
 +++ b/src/gallium/drivers/llvmpipe/lp_state_fs.c
-@@ -3306,6 +3306,7 @@ generate_fragment(struct llvmpipe_context *lp,
+@@ -3320,6 +3320,7 @@ generate_fragment(struct llvmpipe_context *lp,
        LLVMValueRef glob_sample_pos =
           LLVMAddGlobal(gallivm->module,
                         LLVMArrayType(flt_type, key->coverage_samples * 2), "");
@@ -24,6 +21,3 @@ index 2a5977134b0..5a396b44137 100644
        LLVMValueRef sample_pos_array;
  
        if (key->multisample && key->coverage_samples == 4) {
--- 
-2.41.0
-

mesa.spec

@@ -51,7 +51,7 @@
 
 Name:           mesa
 Summary:        Mesa graphics libraries
-Version:        23.1.6
+Version:        23.2.1
 Release:        1
 
 License:        MIT
@@ -571,6 +571,10 @@ done
 %endif
 
 %changelog
+* Thu Nov 02 2023 Jingwiw  <wangjingwei@iscas.ac.cn> - 23.2.1-1
+- upgrade to version 23.2.1
+- fix llvmpipe interface support for the new version
+
 * Sun Aug 20 2023 Funda Wang <fundawang@yeah.net> - 23.1.6-1
 - update to 23.1.6