upgrade to 23.2.1 and fix new interface
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@ -1,32 +1,28 @@
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From 337f91f990070b6a3251550c682fec5ffcce478c Mon Sep 17 00:00:00 2001
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From b4cc97ac05b70fa328ad57cf6defee8113666cac Mon Sep 17 00:00:00 2001
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From: Alex Fan <alex.fan.q@gmail.com>
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From: Alex Fan <alex.fan.q@gmail.com>
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Date: Fri, 29 Jul 2022 12:44:14 +1000
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Date: Fri, 29 Jul 2022 12:44:14 +1000
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Subject: [PATCH] llvmpipe: add riscv support in orcjit
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Subject: [PATCH] llvmpipe: add riscv support in orcjit
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assume cpu supports extension +i,+m,+a,+f,+d,+c
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assume cpu supports extension +i,+m,+a,+f,+d,+c
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---
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---
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.../auxiliary/gallivm/lp_bld_init_orc.cpp | 58 ++++++++++++++++++-
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src/util/detect_arch.h | 16 +++++
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2 files changed, 73 insertions(+), 1 deletion(-)
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diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init_orc.cpp b/src/gallium/auxiliary/gallivm/lp_bld_init_orc.cpp
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diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init_orc.cpp b/src/gallium/auxiliary/gallivm/lp_bld_init_orc.cpp
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index b245edc5586..eaacebd65d6 100644
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index 8ea4df7..91dde78 100644
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--- a/src/gallium/auxiliary/gallivm/lp_bld_init_orc.cpp
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--- a/src/gallium/auxiliary/gallivm/lp_bld_init_orc.cpp
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+++ b/src/gallium/auxiliary/gallivm/lp_bld_init_orc.cpp
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+++ b/src/gallium/auxiliary/gallivm/lp_bld_init_orc.cpp
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@@ -48,7 +48,7 @@
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@@ -44,7 +44,7 @@
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/* conflict with ObjectLinkingLayer.h */
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/* conflict with ObjectLinkingLayer.h */
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#include "util/u_memory.h"
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#include "util/u_memory.h"
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-#if (defined(_WIN32) && LLVM_VERSION_MAJOR >= 15)
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-#if (defined(_WIN32) && LLVM_VERSION_MAJOR >= 15)
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+#if DETECT_ARCH_RISCV64 || DETECT_ARCH_RISCV32 || (defined(_WIN32) && LLVM_VERSION_MAJOR >= 15)
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+#if defined(PIPE_ARCH_RISCV64) || defined(PIPE_ARCH_RISCV32) || (defined(_WIN32) && LLVM_VERSION_MAJOR >= 15)
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/* use ObjectLinkingLayer (JITLINK backend) */
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/* use ObjectLinkingLayer (JITLINK backend) */
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#define USE_JITLINK
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#define USE_JITLINK
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#endif
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#endif
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@@ -521,6 +521,30 @@ llvm::orc::JITTargetMachineBuilder LPJit::create_jtdb() {
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@@ -551,6 +551,30 @@ llvm::orc::JITTargetMachineBuilder LPJit::create_jtdb() {
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options.StackAlignmentOverride = 4;
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options.StackAlignmentOverride = 4;
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#endif
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#endif
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+#if DETECT_ARCH_RISCV64
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+#if defined(PIPE_ARCH_RISCV64)
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+#if defined(__riscv_float_abi_soft)
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+#if defined(__riscv_float_abi_soft)
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+ options.MCOptions.ABIName = "lp64";
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+ options.MCOptions.ABIName = "lp64";
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+#elif defined(__riscv_float_abi_single)
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+#elif defined(__riscv_float_abi_single)
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@ -38,7 +34,7 @@ index b245edc5586..eaacebd65d6 100644
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+#endif
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+#endif
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+#endif
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+#endif
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+
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+
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+#if DETECT_ARCH_RISCV32
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+#if defined(PIPE_ARCH_RISCV32)
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+#if defined(__riscv_float_abi_soft)
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+#if defined(__riscv_float_abi_soft)
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+ options.MCOptions.ABIName = "ilp32";
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+ options.MCOptions.ABIName = "ilp32";
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+#elif defined(__riscv_float_abi_single)
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+#elif defined(__riscv_float_abi_single)
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@ -53,11 +49,11 @@ index b245edc5586..eaacebd65d6 100644
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JTMB.setOptions(options);
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JTMB.setOptions(options);
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std::vector<std::string> MAttrs;
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std::vector<std::string> MAttrs;
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@@ -619,6 +643,14 @@ llvm::orc::JITTargetMachineBuilder LPJit::create_jtdb() {
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@@ -649,6 +673,14 @@ llvm::orc::JITTargetMachineBuilder LPJit::create_jtdb() {
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MAttrs.push_back("+fp64");
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MAttrs.push_back("+fp64");
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#endif
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#endif
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+#if DETECT_ARCH_RISCV64
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+#if defined(PIPE_ARCH_RISCV64)
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+ /* Before riscv is more matured and util_get_cpu_caps() is implemented,
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+ /* Before riscv is more matured and util_get_cpu_caps() is implemented,
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+ * assume this for now since most of linux capable riscv machine are
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+ * assume this for now since most of linux capable riscv machine are
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+ * riscv64gc
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+ * riscv64gc
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@ -67,12 +63,12 @@ index b245edc5586..eaacebd65d6 100644
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+
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+
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JTMB.addFeatures(MAttrs);
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JTMB.addFeatures(MAttrs);
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if (gallivm_debug & (GALLIVM_DEBUG_IR | GALLIVM_DEBUG_ASM | GALLIVM_DEBUG_DUMP_BC)) {
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if (::gallivm_debug & (GALLIVM_DEBUG_IR | GALLIVM_DEBUG_ASM | GALLIVM_DEBUG_DUMP_BC)) {
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@@ -686,6 +718,30 @@ llvm::orc::JITTargetMachineBuilder LPJit::create_jtdb() {
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@@ -716,6 +748,30 @@ llvm::orc::JITTargetMachineBuilder LPJit::create_jtdb() {
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MCPU = util_get_cpu_caps()->has_msa ? "mips64r5" : "mips64r2";
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MCPU = util_get_cpu_caps()->has_msa ? "mips64r5" : "mips64r2";
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#endif
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#endif
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+#if DETECT_ARCH_RISCV64
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+#if defined(PIPE_ARCH_RISCV64)
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+ /**
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+ /**
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+ * should be fixed with https://reviews.llvm.org/D121149 in llvm 15,
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+ * should be fixed with https://reviews.llvm.org/D121149 in llvm 15,
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+ * set it anyway for llvm 14
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+ * set it anyway for llvm 14
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@ -84,7 +80,7 @@ index b245edc5586..eaacebd65d6 100644
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+ JTMB.setRelocationModel(Reloc::PIC_);
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+ JTMB.setRelocationModel(Reloc::PIC_);
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+#endif
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+#endif
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+
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+
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+#if DETECT_ARCH_RISCV32
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+#if defined(PIPE_ARCH_RISCV32)
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+ /**
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+ /**
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+ * should be fixed with https://reviews.llvm.org/D121149 in llvm 15,
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+ * should be fixed with https://reviews.llvm.org/D121149 in llvm 15,
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+ * set it anyway for llvm 14
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+ * set it anyway for llvm 14
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@ -100,37 +96,21 @@ index b245edc5586..eaacebd65d6 100644
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if (gallivm_debug & (GALLIVM_DEBUG_IR | GALLIVM_DEBUG_ASM | GALLIVM_DEBUG_DUMP_BC)) {
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if (gallivm_debug & (GALLIVM_DEBUG_IR | GALLIVM_DEBUG_ASM | GALLIVM_DEBUG_DUMP_BC)) {
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debug_printf("llc -mcpu option: %s\n", MCPU.c_str());
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debug_printf("llc -mcpu option: %s\n", MCPU.c_str());
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diff --git a/src/util/detect_arch.h b/src/util/detect_arch.h
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diff --git a/src/util/detect_arch.h b/src/util/detect_arch.h
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index 334358fcc26..34c0928216d 100644
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index 334358f..8c7bd15 100644
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--- a/src/util/detect_arch.h
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--- a/src/util/detect_arch.h
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+++ b/src/util/detect_arch.h
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+++ b/src/util/detect_arch.h
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@@ -97,6 +97,14 @@
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@@ -137,4 +137,14 @@
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#define DETECT_ARCH_MIPS 1
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#define DETECT_ARCH_MIPS 0
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#endif
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#endif
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+#if defined(__riscv)
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+#if defined(__riscv)
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+#if __riscv_xlen == 64
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+#if __riscv_xlen == 64
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+#define DETECT_ARCH_RISCV64 1
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+#define PIPE_ARCH_RISCV64
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+#elif __riscv_xlen == 32
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+#elif __riscv_xlen == 32
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+#define DETECT_ARCH_RISCV32 1
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+#define PIPE_ARCH_RISCV32
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+#else
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+#error "pipe: unknown target riscv xlen"
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+#endif
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+#endif
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+#endif
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+#endif
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+
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#ifndef DETECT_ARCH_X86
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#define DETECT_ARCH_X86 0
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#endif
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@@ -137,4 +145,12 @@
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#define DETECT_ARCH_MIPS 0
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#endif
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+#ifndef DETECT_ARCH_RISCV32
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+#define DETECT_ARCH_RISCV32 0
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+#endif
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+
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+#ifndef DETECT_ARCH_RISCV64
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+#define DETECT_ARCH_RISCV64 0
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+#endif
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+
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+
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#endif /* UTIL_DETECT_ARCH_H_ */
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#endif /* UTIL_DETECT_ARCH_H_ */
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--
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2.41.0
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@ -9,14 +9,11 @@ changing to internal linkage is safe
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Signed-off-by: Alex Fan <alex.fan.q@gmail.com>
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Signed-off-by: Alex Fan <alex.fan.q@gmail.com>
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---
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---
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src/gallium/drivers/llvmpipe/lp_state_fs.c | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/src/gallium/drivers/llvmpipe/lp_state_fs.c b/src/gallium/drivers/llvmpipe/lp_state_fs.c
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diff --git a/src/gallium/drivers/llvmpipe/lp_state_fs.c b/src/gallium/drivers/llvmpipe/lp_state_fs.c
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index 2a5977134b0..5a396b44137 100644
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index 4e0b693..5b29610 100644
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--- a/src/gallium/drivers/llvmpipe/lp_state_fs.c
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--- a/src/gallium/drivers/llvmpipe/lp_state_fs.c
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+++ b/src/gallium/drivers/llvmpipe/lp_state_fs.c
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+++ b/src/gallium/drivers/llvmpipe/lp_state_fs.c
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@@ -3306,6 +3306,7 @@ generate_fragment(struct llvmpipe_context *lp,
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@@ -3320,6 +3320,7 @@ generate_fragment(struct llvmpipe_context *lp,
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LLVMValueRef glob_sample_pos =
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LLVMValueRef glob_sample_pos =
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LLVMAddGlobal(gallivm->module,
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LLVMAddGlobal(gallivm->module,
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LLVMArrayType(flt_type, key->coverage_samples * 2), "");
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LLVMArrayType(flt_type, key->coverage_samples * 2), "");
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@ -24,6 +21,3 @@ index 2a5977134b0..5a396b44137 100644
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LLVMValueRef sample_pos_array;
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LLVMValueRef sample_pos_array;
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if (key->multisample && key->coverage_samples == 4) {
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if (key->multisample && key->coverage_samples == 4) {
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--
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2.41.0
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Binary file not shown.
@ -51,7 +51,7 @@
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Name: mesa
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Name: mesa
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Summary: Mesa graphics libraries
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Summary: Mesa graphics libraries
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Version: 23.1.6
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Version: 23.2.1
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Release: 1
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Release: 1
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License: MIT
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License: MIT
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@ -571,6 +571,10 @@ done
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%endif
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%endif
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%changelog
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%changelog
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* Thu Nov 02 2023 Jingwiw <wangjingwei@iscas.ac.cn> - 23.2.1-1
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- upgrade to version 23.2.1
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- fix llvmpipe interface support for the new version
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* Sun Aug 20 2023 Funda Wang <fundawang@yeah.net> - 23.1.6-1
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* Sun Aug 20 2023 Funda Wang <fundawang@yeah.net> - 23.1.6-1
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- update to 23.1.6
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- update to 23.1.6
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