add OrcJIT and more backend

2023-08-08 11:32:34 +08:00 · 2023-08-08 11:32:34 +08:00 · 7f92fed407
commit 7f92fed407
parent 5043441786
4 changed files with 2620 additions and 13 deletions
--- a/llvmpipe-add-an-implementation-with-llvm-orcjit.patch
+++ b/llvmpipe-add-an-implementation-with-llvm-orcjit.patch
--- a/llvmpipe-add-riscv-support-in-orcjit.patch
+++ b/llvmpipe-add-riscv-support-in-orcjit.patch
@ -0,0 +1,136 @@
+From 337f91f990070b6a3251550c682fec5ffcce478c Mon Sep 17 00:00:00 2001
+From: Alex Fan <alex.fan.q@gmail.com>
+Date: Fri, 29 Jul 2022 12:44:14 +1000
+Subject: [PATCH] llvmpipe: add riscv support in orcjit
+
+assume cpu supports extension +i,+m,+a,+f,+d,+c
+---
+ .../auxiliary/gallivm/lp_bld_init_orc.cpp     | 58 ++++++++++++++++++-
+ src/util/detect_arch.h                        | 16 +++++
+ 2 files changed, 73 insertions(+), 1 deletion(-)
+
+diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init_orc.cpp b/src/gallium/auxiliary/gallivm/lp_bld_init_orc.cpp
+index b245edc5586..eaacebd65d6 100644
+--- a/src/gallium/auxiliary/gallivm/lp_bld_init_orc.cpp
+++ b/src/gallium/auxiliary/gallivm/lp_bld_init_orc.cpp
+@@ -48,7 +48,7 @@
+ /* conflict with ObjectLinkingLayer.h */
+ #include "util/u_memory.h"
+ 
+-#if (defined(_WIN32) && LLVM_VERSION_MAJOR >= 15)
+#if DETECT_ARCH_RISCV64 || DETECT_ARCH_RISCV32 || (defined(_WIN32) && LLVM_VERSION_MAJOR >= 15)
+ /* use ObjectLinkingLayer (JITLINK backend) */
+ #define USE_JITLINK
+ #endif
+@@ -521,6 +521,30 @@ llvm::orc::JITTargetMachineBuilder LPJit::create_jtdb() {
+    options.StackAlignmentOverride = 4;
+ #endif
+ 
+#if DETECT_ARCH_RISCV64
+#if defined(__riscv_float_abi_soft)
+   options.MCOptions.ABIName = "lp64";
+#elif defined(__riscv_float_abi_single)
+   options.MCOptions.ABIName = "lp64f";
+#elif defined(__riscv_float_abi_double)
+   options.MCOptions.ABIName = "lp64d";
+#else
+#error "GALLIVM: unknown target riscv float abi"
+#endif
+#endif
+
+#if DETECT_ARCH_RISCV32
+#if defined(__riscv_float_abi_soft)
+   options.MCOptions.ABIName = "ilp32";
+#elif defined(__riscv_float_abi_single)
+   options.MCOptions.ABIName = "ilp32f";
+#elif defined(__riscv_float_abi_double)
+   options.MCOptions.ABIName = "ilp32d";
+#else
+#error "GALLIVM: unknown target riscv float abi"
+#endif
+#endif
+
+    JTMB.setOptions(options);
+ 
+    std::vector<std::string> MAttrs;
+@@ -619,6 +643,14 @@ llvm::orc::JITTargetMachineBuilder LPJit::create_jtdb() {
+    MAttrs.push_back("+fp64");
+ #endif
+ 
+#if DETECT_ARCH_RISCV64
+   /* Before riscv is more matured and util_get_cpu_caps() is implemented,
+    * assume this for now since most of linux capable riscv machine are
+    * riscv64gc
+    */
+   MAttrs = {"+m","+c","+a","+d","+f"};
+#endif
+
+    JTMB.addFeatures(MAttrs);
+ 
+    if (gallivm_debug & (GALLIVM_DEBUG_IR | GALLIVM_DEBUG_ASM | GALLIVM_DEBUG_DUMP_BC)) {
+@@ -686,6 +718,30 @@ llvm::orc::JITTargetMachineBuilder LPJit::create_jtdb() {
+       MCPU = util_get_cpu_caps()->has_msa ? "mips64r5" : "mips64r2";
+ #endif
+ 
+#if DETECT_ARCH_RISCV64
+   /**
+    * should be fixed with https://reviews.llvm.org/D121149 in llvm 15,
+    * set it anyway for llvm 14
+    */
+   if (MCPU == "generic")
+      MCPU = "generic-rv64";
+
+   JTMB.setCodeModel(CodeModel::Medium);
+   JTMB.setRelocationModel(Reloc::PIC_);
+#endif
+
+#if DETECT_ARCH_RISCV32
+   /**
+    * should be fixed with https://reviews.llvm.org/D121149 in llvm 15,
+    * set it anyway for llvm 14
+    */
+   if (MCPU == "generic")
+      MCPU = "generic-rv32";
+
+   JTMB.setCodeModel(CodeModel::Medium);
+   JTMB.setRelocationModel(Reloc::PIC_);
+#endif
+
+    JTMB.setCPU(MCPU);
+    if (gallivm_debug & (GALLIVM_DEBUG_IR | GALLIVM_DEBUG_ASM | GALLIVM_DEBUG_DUMP_BC)) {
+       debug_printf("llc -mcpu option: %s\n", MCPU.c_str());
+diff --git a/src/util/detect_arch.h b/src/util/detect_arch.h
+index 334358fcc26..34c0928216d 100644
+--- a/src/util/detect_arch.h
+++ b/src/util/detect_arch.h
+@@ -97,6 +97,14 @@
+ #define DETECT_ARCH_MIPS 1
+ #endif
+ 
+#if defined(__riscv)
+#if __riscv_xlen == 64
+#define DETECT_ARCH_RISCV64 1
+#elif __riscv_xlen == 32
+#define DETECT_ARCH_RISCV32 1
+#endif
+#endif
+
+ #ifndef DETECT_ARCH_X86
+ #define DETECT_ARCH_X86 0
+ #endif
+@@ -137,4 +145,12 @@
+ #define DETECT_ARCH_MIPS 0
+ #endif
+ 
+#ifndef DETECT_ARCH_RISCV32
+#define DETECT_ARCH_RISCV32 0
+#endif
+
+#ifndef DETECT_ARCH_RISCV64
+#define DETECT_ARCH_RISCV64 0
+#endif
+
+ #endif /* UTIL_DETECT_ARCH_H_ */
+-- 
+2.41.0
+
--- a/llvmpipe-make-unnamed-global-have-internal-linkage.patch
+++ b/llvmpipe-make-unnamed-global-have-internal-linkage.patch
@ -0,0 +1,29 @@
+From 3148f08bd0207a8bd50ff5c8b82d7a5b0871c3d1 Mon Sep 17 00:00:00 2001
+From: Alex Fan <alex.fan.q@gmail.com>
+Date: Mon, 28 Nov 2022 22:29:44 +1100
+Subject: [PATCH] llvmpipe: make unnamed global have internal linkage
+
+work around bug https://github.com/llvm/llvm-project/issues/54813
+Being unnamed makes it not useable from other module, therefore
+changing to internal linkage is safe
+
+Signed-off-by: Alex Fan <alex.fan.q@gmail.com>
+---
+ src/gallium/drivers/llvmpipe/lp_state_fs.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/src/gallium/drivers/llvmpipe/lp_state_fs.c b/src/gallium/drivers/llvmpipe/lp_state_fs.c
+index 2a5977134b0..5a396b44137 100644
+--- a/src/gallium/drivers/llvmpipe/lp_state_fs.c
+++ b/src/gallium/drivers/llvmpipe/lp_state_fs.c
+@@ -3306,6 +3306,7 @@ generate_fragment(struct llvmpipe_context *lp,
+       LLVMValueRef glob_sample_pos =
+          LLVMAddGlobal(gallivm->module,
+                        LLVMArrayType(flt_type, key->coverage_samples * 2), "");
+      LLVMSetLinkage(glob_sample_pos, LLVMInternalLinkage);
+       LLVMValueRef sample_pos_array;
+ 
+       if (key->multisample && key->coverage_samples == 4) {
+-- 
+2.41.0
+
--- a/mesa.spec
+++ b/mesa.spec
@ -6,6 +6,8 @@
 %else
 %define with_hardware 1
 %define with_vdpau 1
+%define with_omx 1
+%define with_nine 1
 %endif

 %ifarch %{ix86} x86_64
@ -13,6 +15,7 @@
 %define with_vmware 1
 %define with_xa     1
 %define with_iris   1
+%define with_crocus 1
 %endif

 %ifarch %{ix86} x86_64
@ -25,12 +28,17 @@
 %define with_xa        1
 %endif

+%ifarch riscv64
+%define with_xa        1
+%define with_vmware    1
+%endif
+
 %global dri_drivers %{?platform_drivers}

 %if 0%{?with_vulkan_hw}
-%define vulkan_drivers swrast,intel,amd
+%define vulkan_drivers swrast,intel,amd,intel_hasvk
 %else
-%define vulkan_drivers swrast
+%define vulkan_drivers swrast,amd
 %endif

 %global sanitize 0
@ -38,7 +46,7 @@
 Name:           mesa
 Summary:        Mesa graphics libraries
 Version:        23.1.3
-Release:        1
+Release:        2

 License:        MIT
 URL:            http://www.mesa3d.org
@ -46,11 +54,14 @@ Source0:        https://mesa.freedesktop.org/archive/%{name}-%{version}.tar.xz

 Patch1:         backport-fix-build-err-on-arm.patch
 Patch2:         0001-evergreen-big-endian.patch
+Patch3:         llvmpipe-add-an-implementation-with-llvm-orcjit.patch
+Patch4:         llvmpipe-add-riscv-support-in-orcjit.patch
+Patch5:         llvmpipe-make-unnamed-global-have-internal-linkage.patch

 BuildRequires:  gcc
 BuildRequires:  gcc-c++

-BuildRequires:  meson >= 0.45
+BuildRequires:  meson >= 1.0.0
 %if %{with_hardware}
 BuildRequires:  kernel-headers
 %endif
@ -304,7 +315,7 @@ export ASFLAGS="--generate-missing-build-notes=yes"
  -Ddri3=enabled \
  -Dosmesa=true \
 %if 0%{?with_hardware}
-  -Dgallium-drivers=swrast%{?with_iris:,iris},virgl,nouveau%{?with_vmware:,svga},radeonsi,r600%{?with_freedreno:,freedreno}%{?with_etnaviv:,etnaviv}%{?with_tegra:,tegra}%{?with_vc4:,vc4}%{?with_kmsro:,kmsro} \
+  -Dgallium-drivers=swrast%{?with_iris:,iris},virgl,nouveau%{?with_vmware:,svga},radeonsi,r300,r600%{?with_freedreno:,freedreno}%{?with_etnaviv:,etnaviv}%{?with_tegra:,tegra}%{?with_vc4:,vc4}%{?with_kmsro:,kmsro}%{?with_crocus:,crocus} \
 %else
  -Dgallium-drivers=swrast,virgl \
 %endif
@ -461,9 +472,11 @@ done
 %dir %{_datadir}/drirc.d
 %{_datadir}/drirc.d/00-mesa-defaults.conf
 %if %{with_hardware}
+%{_libdir}/dri/r300_dri.so
 %{_libdir}/dri/r600_dri.so
 %{_libdir}/dri/radeonsi_dri.so
 %ifarch %{ix86} x86_64
+%{_libdir}/dri/crocus_dri.so
 %{_libdir}/dri/iris_dri.so
 %endif
 %if 0%{?with_vc4}
@ -496,6 +509,7 @@ done
 %{_libdir}/vdpau/libvdpau_nouveau.so.1*
 %{_libdir}/vdpau/libvdpau_r600.so.1*
 %{_libdir}/vdpau/libvdpau_radeonsi.so.1*
+%{_libdir}/vdpau/libvdpau_virtio_gpu.so.1*
 %endif
 %endif

@ -503,16 +517,14 @@ done
 %if 0%{?with_vulkan_hw}
 %{_libdir}/libvulkan_intel.so
 %{_libdir}/libvulkan_radeon.so
-%ifarch x86_64
+%{_libdir}/libvulkan_intel_hasvk.so
+%{_datadir}/vulkan/icd.d/intel_hasvk_icd.*.json
+%{_datadir}/vulkan/icd.d/intel_icd.*.json
+%endif
 %{_datadir}/drirc.d/00-radv-defaults.conf
-%{_datadir}/vulkan/icd.d/intel_icd.x86_64.json
-%{_datadir}/vulkan/icd.d/radeon_icd.x86_64.json
-%else
-%{_datadir}/vulkan/icd.d/intel_icd.i686.json
-%{_datadir}/vulkan/icd.d/radeon_icd.i686.json
-%endif
-%endif
+%{_datadir}/vulkan/icd.d/radeon_icd.*.json
 %{_libdir}/vdpau/libvdpau_virtio_gpu.so.1*
+%{_libdir}/libvulkan_radeon.so
 %{_libdir}/libvulkan_lvp.so
 %{_datadir}/vulkan/icd.d/lvp_icd.*.json
 %{_libdir}/libVkLayer_MESA_device_select.so
@ -523,6 +535,10 @@ done
 %endif

 %changelog
+* Tue Aug 08 2023 Jingwiw  <wangjingwei@iscas.ac.cn> - 23.1.3-2
+- Add OrcJIT and add riscv architecture optimization
+- Optimize the mesa spec and add more backend
+
 * Mon Jul 31 2023 zhouwenpei <zhouwenpei1@h-partners.com> - 23.1.3-1
 - upgrade to mesa-23.1.3