363 lines
14 KiB
Diff
363 lines
14 KiB
Diff
From 87f6adc2acf635a0a4c294217fb54c55eee3a06c Mon Sep 17 00:00:00 2001
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From: Jinyang He <hejinyang@loongson.cn>
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Date: Wed, 24 Jan 2024 09:17:49 +0800
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Subject: [PATCH 08/14] [LoongArch] Insert nops and emit align reloc when
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handle alignment directive (#72962)
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Refer to RISCV, we will fix up the alignment if linker relaxation
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changes code size and breaks alignment. Insert enough Nops and emit
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R_LARCH_ALIGN relocation type so that linker could satisfy the alignment
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by removing Nops.
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It does so only in sections with the SHF_EXECINSTR flag.
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In LoongArch psABI v2.30, R_LARCH_ALIGN requires symbol index. The
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lowest 8 bits of addend represent alignment and the other bits of addend
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represent the maximum number of bytes to emit.
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(cherry picked from commit c51ab483e6c2d991a01179584705b83fbea1940d)
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Change-Id: Iba30702c9dda378acfae0b1f1134926fa838a368
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---
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llvm/lib/MC/MCExpr.cpp | 2 +-
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.../MCTargetDesc/LoongArchAsmBackend.cpp | 67 ++++++++++++++++
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.../MCTargetDesc/LoongArchAsmBackend.h | 15 ++++
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.../MCTargetDesc/LoongArchFixupKinds.h | 4 +-
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.../Relocations/align-non-executable.s | 27 +++++++
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.../MC/LoongArch/Relocations/relax-addsub.s | 15 +++-
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.../MC/LoongArch/Relocations/relax-align.s | 79 +++++++++++++++++++
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7 files changed, 205 insertions(+), 4 deletions(-)
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create mode 100644 llvm/test/MC/LoongArch/Relocations/align-non-executable.s
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create mode 100644 llvm/test/MC/LoongArch/Relocations/relax-align.s
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diff --git a/llvm/lib/MC/MCExpr.cpp b/llvm/lib/MC/MCExpr.cpp
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index a561fed11179..79808a58d81c 100644
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--- a/llvm/lib/MC/MCExpr.cpp
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+++ b/llvm/lib/MC/MCExpr.cpp
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@@ -711,7 +711,7 @@ static void AttemptToFoldSymbolOffsetDifference(
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if (DF) {
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Displacement += DF->getContents().size();
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} else if (auto *AF = dyn_cast<MCAlignFragment>(FI);
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- AF && Layout &&
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+ AF && Layout && AF->hasEmitNops() &&
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!Asm->getBackend().shouldInsertExtraNopBytesForCodeAlign(
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*AF, Count)) {
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Displacement += Asm->computeFragmentSize(*Layout, *AF);
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diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
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index 8d82327b2e2b..8c482356402f 100644
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--- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
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+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
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@@ -17,10 +17,13 @@
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#include "llvm/MC/MCAssembler.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCELFObjectWriter.h"
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+#include "llvm/MC/MCExpr.h"
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+#include "llvm/MC/MCSection.h"
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#include "llvm/MC/MCValue.h"
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#include "llvm/Support/Endian.h"
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#include "llvm/Support/EndianStream.h"
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#include "llvm/Support/LEB128.h"
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+#include "llvm/Support/MathExtras.h"
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#define DEBUG_TYPE "loongarch-asmbackend"
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@@ -177,6 +180,70 @@ void LoongArchAsmBackend::applyFixup(const MCAssembler &Asm,
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}
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}
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+// Linker relaxation may change code size. We have to insert Nops
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+// for .align directive when linker relaxation enabled. So then Linker
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+// could satisfy alignment by removing Nops.
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+// The function returns the total Nops Size we need to insert.
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+bool LoongArchAsmBackend::shouldInsertExtraNopBytesForCodeAlign(
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+ const MCAlignFragment &AF, unsigned &Size) {
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+ // Calculate Nops Size only when linker relaxation enabled.
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+ if (!AF.getSubtargetInfo()->hasFeature(LoongArch::FeatureRelax))
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+ return false;
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+
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+ // Ignore alignment if MaxBytesToEmit is less than the minimum Nop size.
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+ const unsigned MinNopLen = 4;
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+ if (AF.getMaxBytesToEmit() < MinNopLen)
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+ return false;
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+ Size = AF.getAlignment().value() - MinNopLen;
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+ return AF.getAlignment() > MinNopLen;
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+}
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+
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+// We need to insert R_LARCH_ALIGN relocation type to indicate the
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+// position of Nops and the total bytes of the Nops have been inserted
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+// when linker relaxation enabled.
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+// The function inserts fixup_loongarch_align fixup which eventually will
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+// transfer to R_LARCH_ALIGN relocation type.
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+// The improved R_LARCH_ALIGN requires symbol index. The lowest 8 bits of
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+// addend represent alignment and the other bits of addend represent the
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+// maximum number of bytes to emit. The maximum number of bytes is zero
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+// means ignore the emit limit.
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+bool LoongArchAsmBackend::shouldInsertFixupForCodeAlign(
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+ MCAssembler &Asm, const MCAsmLayout &Layout, MCAlignFragment &AF) {
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+ // Insert the fixup only when linker relaxation enabled.
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+ if (!AF.getSubtargetInfo()->hasFeature(LoongArch::FeatureRelax))
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+ return false;
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+
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+ // Calculate total Nops we need to insert. If there are none to insert
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+ // then simply return.
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+ unsigned Count;
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+ if (!shouldInsertExtraNopBytesForCodeAlign(AF, Count))
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+ return false;
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+
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+ MCSection *Sec = AF.getParent();
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+ MCContext &Ctx = Asm.getContext();
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+ const MCExpr *Dummy = MCConstantExpr::create(0, Ctx);
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+ // Create fixup_loongarch_align fixup.
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+ MCFixup Fixup =
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+ MCFixup::create(0, Dummy, MCFixupKind(LoongArch::fixup_loongarch_align));
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+ const MCSymbolRefExpr *MCSym = getSecToAlignSym()[Sec];
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+ if (MCSym == nullptr) {
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+ // Create a symbol and make the value of symbol is zero.
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+ MCSymbol *Sym = Ctx.createNamedTempSymbol("la-relax-align");
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+ Sym->setFragment(&*Sec->getBeginSymbol()->getFragment());
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+ Asm.registerSymbol(*Sym);
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+ MCSym = MCSymbolRefExpr::create(Sym, Ctx);
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+ getSecToAlignSym()[Sec] = MCSym;
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+ }
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+
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+ uint64_t FixedValue = 0;
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+ unsigned Lo = Log2_64(Count) + 1;
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+ unsigned Hi = AF.getMaxBytesToEmit() >= Count ? 0 : AF.getMaxBytesToEmit();
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+ MCValue Value = MCValue::get(MCSym, nullptr, Hi << 8 | Lo);
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+ Asm.getWriter().recordRelocation(Asm, Layout, &AF, Fixup, Value, FixedValue);
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+
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+ return true;
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+}
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+
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bool LoongArchAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
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const MCFixup &Fixup,
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const MCValue &Target) {
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diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h
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index 657f5ca5e731..71bbd003888a 100644
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--- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h
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+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h
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@@ -17,7 +17,9 @@
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#include "MCTargetDesc/LoongArchFixupKinds.h"
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#include "MCTargetDesc/LoongArchMCTargetDesc.h"
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#include "llvm/MC/MCAsmBackend.h"
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+#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCFixupKindInfo.h"
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+#include "llvm/MC/MCSection.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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namespace llvm {
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@@ -27,6 +29,7 @@ class LoongArchAsmBackend : public MCAsmBackend {
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uint8_t OSABI;
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bool Is64Bit;
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const MCTargetOptions &TargetOptions;
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+ DenseMap<MCSection *, const MCSymbolRefExpr *> SecToAlignSym;
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public:
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LoongArchAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit,
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@@ -45,6 +48,15 @@ public:
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uint64_t Value, bool IsResolved,
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const MCSubtargetInfo *STI) const override;
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+ // Return Size with extra Nop Bytes for alignment directive in code section.
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+ bool shouldInsertExtraNopBytesForCodeAlign(const MCAlignFragment &AF,
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+ unsigned &Size) override;
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+
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+ // Insert target specific fixup type for alignment directive in code section.
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+ bool shouldInsertFixupForCodeAlign(MCAssembler &Asm,
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+ const MCAsmLayout &Layout,
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+ MCAlignFragment &AF) override;
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+
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bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
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const MCValue &Target) override;
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@@ -79,6 +91,9 @@ public:
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std::unique_ptr<MCObjectTargetWriter>
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createObjectTargetWriter() const override;
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const MCTargetOptions &getTargetOptions() const { return TargetOptions; }
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+ DenseMap<MCSection *, const MCSymbolRefExpr *> &getSecToAlignSym() {
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+ return SecToAlignSym;
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+ }
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};
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} // end namespace llvm
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diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchFixupKinds.h b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchFixupKinds.h
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index 178fa6e5262b..78414408f21f 100644
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--- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchFixupKinds.h
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+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchFixupKinds.h
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@@ -108,7 +108,9 @@ enum Fixups {
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// 20-bit fixup corresponding to %gd_hi20(foo) for instruction lu12i.w.
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fixup_loongarch_tls_gd_hi20,
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// Generate an R_LARCH_RELAX which indicates the linker may relax here.
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- fixup_loongarch_relax = FirstLiteralRelocationKind + ELF::R_LARCH_RELAX
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+ fixup_loongarch_relax = FirstLiteralRelocationKind + ELF::R_LARCH_RELAX,
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+ // Generate an R_LARCH_ALIGN which indicates the linker may fixup align here.
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+ fixup_loongarch_align = FirstLiteralRelocationKind + ELF::R_LARCH_ALIGN,
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};
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} // end namespace LoongArch
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} // end namespace llvm
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diff --git a/llvm/test/MC/LoongArch/Relocations/align-non-executable.s b/llvm/test/MC/LoongArch/Relocations/align-non-executable.s
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new file mode 100644
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index 000000000000..47834acd9521
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--- /dev/null
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+++ b/llvm/test/MC/LoongArch/Relocations/align-non-executable.s
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@@ -0,0 +1,27 @@
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+## A label difference separated by an alignment directive, when the
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+## referenced symbols are in a non-executable section with instructions,
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+## should generate ADD/SUB relocations.
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+## https://github.com/llvm/llvm-project/pull/76552
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+
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+# RUN: llvm-mc --filetype=obj --triple=loongarch64 --mattr=+relax %s \
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+# RUN: | llvm-readobj -r - | FileCheck --check-prefixes=CHECK,RELAX %s
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+# RUN: llvm-mc --filetype=obj --triple=loongarch64 --mattr=-relax %s \
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+# RUN: | llvm-readobj -r - | FileCheck %s
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+
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+.section ".dummy", "a"
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+.L1:
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+ la.pcrel $t0, sym
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+.p2align 3
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+.L2:
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+.dword .L2 - .L1
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+
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+# CHECK: Relocations [
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+# CHECK-NEXT: Section ({{.*}}) .rela.dummy {
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+# CHECK-NEXT: 0x0 R_LARCH_PCALA_HI20 sym 0x0
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+# RELAX-NEXT: 0x0 R_LARCH_RELAX - 0x0
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+# CHECK-NEXT: 0x4 R_LARCH_PCALA_LO12 sym 0x0
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+# RELAX-NEXT: 0x4 R_LARCH_RELAX - 0x0
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+# RELAX-NEXT: 0x8 R_LARCH_ADD64 .L2 0x0
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+# RELAX-NEXT: 0x8 R_LARCH_SUB64 .L1 0x0
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+# CHECK-NEXT: }
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+# CHECK-NEXT: ]
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diff --git a/llvm/test/MC/LoongArch/Relocations/relax-addsub.s b/llvm/test/MC/LoongArch/Relocations/relax-addsub.s
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index cd01332afd0b..18e0ede5e293 100644
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--- a/llvm/test/MC/LoongArch/Relocations/relax-addsub.s
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+++ b/llvm/test/MC/LoongArch/Relocations/relax-addsub.s
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@@ -28,12 +28,23 @@
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# RELAX: Relocations [
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# RELAX-NEXT: Section ({{.*}}) .rela.text {
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+# RELAX-NEXT: 0x4 R_LARCH_ALIGN {{.*}} 0x4
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# RELAX-NEXT: 0x10 R_LARCH_PCALA_HI20 .L1 0x0
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# RELAX-NEXT: 0x10 R_LARCH_RELAX - 0x0
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# RELAX-NEXT: 0x14 R_LARCH_PCALA_LO12 .L1 0x0
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# RELAX-NEXT: 0x14 R_LARCH_RELAX - 0x0
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# RELAX-NEXT: }
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# RELAX-NEXT: Section ({{.*}}) .rela.data {
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+# RELAX-NEXT: 0x10 R_LARCH_ADD8 .L3 0x0
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+# RELAX-NEXT: 0x10 R_LARCH_SUB8 .L2 0x0
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+# RELAX-NEXT: 0x11 R_LARCH_ADD16 .L3 0x0
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+# RELAX-NEXT: 0x11 R_LARCH_SUB16 .L2 0x0
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+# RELAX-NEXT: 0x13 R_LARCH_ADD32 .L3 0x0
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+# RELAX-NEXT: 0x13 R_LARCH_SUB32 .L2 0x0
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+# RELAX-NEXT: 0x17 R_LARCH_ADD64 .L3 0x0
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+# RELAX-NEXT: 0x17 R_LARCH_SUB64 .L2 0x0
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+# RELAX-NEXT: 0x1F R_LARCH_ADD_ULEB128 .L3 0x0
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+# RELAX-NEXT: 0x1F R_LARCH_SUB_ULEB128 .L2 0x0
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# RELAX-NEXT: 0x20 R_LARCH_ADD8 .L4 0x0
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# RELAX-NEXT: 0x20 R_LARCH_SUB8 .L3 0x0
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# RELAX-NEXT: 0x21 R_LARCH_ADD16 .L4 0x0
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@@ -57,7 +68,7 @@
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# RELAX: Hex dump of section '.data':
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# RELAX-NEXT: 0x00000000 04040004 00000004 00000000 00000004
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-# RELAX-NEXT: 0x00000010 0c0c000c 0000000c 00000000 0000000c
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+# RELAX-NEXT: 0x00000010 00000000 00000000 00000000 00000000
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# RELAX-NEXT: 0x00000020 00000000 00000000 00000000 00000000
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# RELAX-NEXT: 0x00000030 00000000 00000000 00000000 000000
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@@ -78,7 +89,7 @@
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.word .L2 - .L1
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.dword .L2 - .L1
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.uleb128 .L2 - .L1
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-## TODO Handle alignment directive.
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+## With relaxation, emit relocs because the .align makes the diff variable.
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.byte .L3 - .L2
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.short .L3 - .L2
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.word .L3 - .L2
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diff --git a/llvm/test/MC/LoongArch/Relocations/relax-align.s b/llvm/test/MC/LoongArch/Relocations/relax-align.s
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new file mode 100644
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index 000000000000..294fd9fb916c
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--- /dev/null
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+++ b/llvm/test/MC/LoongArch/Relocations/relax-align.s
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@@ -0,0 +1,79 @@
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+## The file testing Nop insertion with R_LARCH_ALIGN for relaxation.
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+
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+# RUN: llvm-mc --filetype=obj --triple=loongarch64 --mattr=-relax %s -o %t
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+# RUN: llvm-objdump -d %t | FileCheck %s --check-prefix=INSTR
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+# RUN: llvm-readobj -r %t | FileCheck %s --check-prefix=RELOC
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+# RUN: llvm-mc --filetype=obj --triple=loongarch64 --mattr=+relax %s -o %t.r
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+# RUN: llvm-objdump -d %t.r | FileCheck %s --check-prefixes=INSTR,RELAX-INSTR
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+# RUN: llvm-readobj -r %t.r | FileCheck %s --check-prefixes=RELOC,RELAX-RELOC
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+
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+.text
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+break 0
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+# INSTR: break 0
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+
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+## Not emit R_LARCH_ALIGN if alignment directive is less than or equal to
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+## minimum code alignment(a.k.a 4).
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+.p2align 2
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+.p2align 1
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+.p2align 0
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+
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+## Not emit instructions if max emit bytes less than min nop size.
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+.p2align 4, , 2
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+
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+## Not emit R_LARCH_ALIGN if alignment directive with specific padding value.
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+## The behavior is the same as GNU assembler.
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+break 1
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+.p2align 4, 1
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+# INSTR-NEXT: break 1
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+# INSTR-COUNT-2: 01 01 01 01
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+
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+break 2
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+.p2align 4, 1, 12
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+# INSTR-NEXT: break 2
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+# INSTR-COUNT-3: 01 01 01 01
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+
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+break 3
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+.p2align 4
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+# INSTR-NEXT: break 3
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+# INSTR-COUNT-3: nop
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+
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+break 4
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+.p2align 5
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+.p2align 4
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+# INSTR-NEXT: break 4
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+# INSTR-COUNT-3: nop
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+# RELAX-INSTR-COUNT-7: nop
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+
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+break 5
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+.p2align 4, , 11
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+# INSTR-NEXT: break 5
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+# RELAX-INSTR-COUNT-3: nop
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+
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+break 6
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+## Not emit the third parameter.
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+.p2align 4, , 12
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+# INSTR-NEXT: break 6
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+# INSTR-NEXT: nop
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+# INSTR-NEXT: nop
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+# RELAX-INSTR-NEXT: nop
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+
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+ret
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+# INSNR-NEXT: ret
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+
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+## Test the symbol index is different from .text.
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+.section .text2, "ax"
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+.p2align 4
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+break 7
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+
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+# RELOC: Relocations [
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+# RELAX-RELOC-NEXT: Section ({{.*}}) .rela.text {
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+# RELAX-RELOC-NEXT: 0x24 R_LARCH_ALIGN .Lla-relax-align0 0x4
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+# RELAX-RELOC-NEXT: 0x34 R_LARCH_ALIGN .Lla-relax-align0 0x5
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+# RELAX-RELOC-NEXT: 0x50 R_LARCH_ALIGN .Lla-relax-align0 0x4
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+# RELAX-RELOC-NEXT: 0x60 R_LARCH_ALIGN .Lla-relax-align0 0xB04
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+# RELAX-RELOC-NEXT: 0x70 R_LARCH_ALIGN .Lla-relax-align0 0x4
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+# RELAX-RELOC-NEXT: }
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+# RELAX-RELOC-NEXT: Section ({{.*}}) .rela.text2 {
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+# RELAX-RELOC-NEXT: 0x0 R_LARCH_ALIGN .Lla-relax-align1 0x4
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+# RELAX-RELOC-NEXT: }
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+# RELOC-NEXT: ]
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--
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2.20.1
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