!162 [AArch64] Delete hip09 macro && [backport][Clang] Fix crash with -fzero-call-used-regs
From: @xiajingze Reviewed-by: @eastb233 Signed-off-by: @eastb233
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514
0027-AArch64-Delete-hip09-macro.patch
Normal file
514
0027-AArch64-Delete-hip09-macro.patch
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@ -0,0 +1,514 @@
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From 42b0d16ab1ced5720e017fa9f6059c32489ab1bd Mon Sep 17 00:00:00 2001
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From: xiajingze <xiajingze1@huawei.com>
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Date: Wed, 9 Oct 2024 17:13:49 +0800
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Subject: [PATCH] [AArch64] Delete hip09 macro
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Signed-off-by: xiajingze <xiajingze1@huawei.com>
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---
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llvm/cmake/modules/HandleLLVMOptions.cmake | 8 --
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.../llvm/TargetParser/AArch64TargetParser.h | 2 -
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llvm/lib/Target/AArch64/AArch64.td | 8 --
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.../lib/Target/AArch64/AArch64MacroFusion.cpp | 8 --
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llvm/lib/Target/AArch64/AArch64Subtarget.cpp | 2 -
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llvm/lib/Target/AArch64/AArch64Subtarget.h | 6 --
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llvm/lib/Target/CMakeLists.txt | 4 -
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llvm/lib/TargetParser/Host.cpp | 2 -
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llvm/test/CodeGen/AArch64/cpus-hip09.ll | 11 ---
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llvm/test/CodeGen/AArch64/cpus.ll | 1 +
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.../CodeGen/AArch64/macro-fusion-mvnclz.mir | 1 -
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.../AArch64/misched-fusion-lit-hip09.ll | 73 --------------
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.../CodeGen/AArch64/misched-fusion-lit.ll | 7 ++
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llvm/test/CodeGen/AArch64/remat-hip09.ll | 18 ----
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llvm/test/CodeGen/AArch64/remat.ll | 1 +
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llvm/test/lit.site.cfg.py.in | 4 -
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llvm/unittests/TargetParser/Host.cpp | 2 -
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.../TargetParser/TargetParserTest.cpp | 6 --
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18 files changed, 9 insertions(+), 155 deletions(-)
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delete mode 100644 llvm/test/CodeGen/AArch64/cpus-hip09.ll
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delete mode 100644 llvm/test/CodeGen/AArch64/misched-fusion-lit-hip09.ll
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delete mode 100644 llvm/test/CodeGen/AArch64/remat-hip09.ll
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diff --git a/llvm/cmake/modules/HandleLLVMOptions.cmake b/llvm/cmake/modules/HandleLLVMOptions.cmake
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index 74e68e25d85c..8be5d4ba52c2 100644
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--- a/llvm/cmake/modules/HandleLLVMOptions.cmake
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+++ b/llvm/cmake/modules/HandleLLVMOptions.cmake
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@@ -112,14 +112,6 @@ else()
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set(LLVM_ENABLE_AUTOTUNER 0)
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endif()
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-option(LLVM_ENABLE_AARCH64_HIP09 "Enable HIP09 Processor" ON)
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-if(LLVM_ENABLE_AARCH64_HIP09)
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- set(LLVM_ENABLE_AARCH64_HIP09 1)
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- add_definitions( -DENABLE_AARCH64_HIP09 )
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-else()
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- set(LLVM_ENABLE_AARCH64_HIP09 0)
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-endif()
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-
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if(LLVM_ENABLE_EXPENSIVE_CHECKS)
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add_compile_definitions(EXPENSIVE_CHECKS)
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diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
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index 07cd2fcbb68d..8b25cce0abdc 100644
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--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
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+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
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@@ -542,13 +542,11 @@ inline constexpr CpuInfo CpuInfos[] = {
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(AArch64::AEK_FP16 | AArch64::AEK_RAND | AArch64::AEK_SM4 |
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AArch64::AEK_SHA3 | AArch64::AEK_SHA2 | AArch64::AEK_AES |
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AArch64::AEK_MTE | AArch64::AEK_SB | AArch64::AEK_SSBS)},
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-#if defined(ENABLE_AARCH64_HIP09)
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{"hip09", ARMV8_5A,
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(AArch64::AEK_AES | AArch64::AEK_SM4 | AArch64::AEK_SHA2 |
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AArch64::AEK_SHA3 | AArch64::AEK_FP16 | AArch64::AEK_PROFILE |
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AArch64::AEK_FP16FML | AArch64::AEK_SVE | AArch64::AEK_I8MM |
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AArch64::AEK_F32MM | AArch64::AEK_F64MM | AArch64::AEK_BF16)},
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-#endif
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};
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// An alias for a CPU.
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diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
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index c8bfd770f55f..fdb931a0fe6c 100644
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--- a/llvm/lib/Target/AArch64/AArch64.td
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+++ b/llvm/lib/Target/AArch64/AArch64.td
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@@ -296,11 +296,9 @@ def FeatureFuseAddSub2RegAndConstOne : SubtargetFeature<
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"fuse-addsub-2reg-const1", "HasFuseAddSub2RegAndConstOne", "true",
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"CPU fuses (a + b + 1) and (a - b - 1)">;
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-#ifdef ENABLE_AARCH64_HIP09
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def FeatureFuseMvnClz : SubtargetFeature<
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"fuse-mvn-clz", "HasFuseMvnClz", "true",
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"CPU fuses mvn+clz operations">;
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-#endif
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def FeatureDisableLatencySchedHeuristic : SubtargetFeature<
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"disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
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@@ -1211,7 +1209,6 @@ def TuneTSV110 : SubtargetFeature<"tsv110", "ARMProcFamily", "TSV110",
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FeatureFuseAES,
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FeaturePostRAScheduler]>;
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-#ifdef ENABLE_AARCH64_HIP09
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def TuneHIP09 : SubtargetFeature<"hip09", "ARMProcFamily", "HIP09",
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"HiSilicon HIP-09 processors", [
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FeatureCustomCheapAsMoveHandling,
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@@ -1224,7 +1221,6 @@ def TuneHIP09 : SubtargetFeature<"hip09", "ARMProcFamily", "HIP09",
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FeatureFuseLiterals,
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FeatureFuseMvnClz,
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FeaturePostRAScheduler]>;
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-#endif
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def TuneAmpere1 : SubtargetFeature<"ampere1", "ARMProcFamily", "Ampere1",
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"Ampere Computing Ampere-1 processors", [
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@@ -1380,14 +1376,12 @@ def ProcessorFeatures {
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list<SubtargetFeature> TSV110 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
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FeatureNEON, FeaturePerfMon, FeatureSPE,
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FeatureFullFP16, FeatureFP16FML, FeatureDotProd];
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-#ifdef ENABLE_AARCH64_HIP09
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list<SubtargetFeature> HIP09 = [HasV8_5aOps, FeatureBF16, FeatureCrypto, FeatureFPARMv8,
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FeatureMatMulInt8, FeatureMatMulFP32, FeatureMatMulFP64,
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FeatureNEON, FeaturePerfMon, FeatureRandGen, FeatureSPE,
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FeatureFullFP16, FeatureFP16FML, FeatureDotProd,
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FeatureJS, FeatureComplxNum, FeatureSHA3, FeatureSM4,
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FeatureSVE];
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-#endif
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list<SubtargetFeature> Ampere1 = [HasV8_6aOps, FeatureNEON, FeaturePerfMon,
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FeatureSSBS, FeatureRandGen, FeatureSB,
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FeatureSHA2, FeatureSHA3, FeatureAES];
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@@ -1497,11 +1491,9 @@ def : ProcessorModel<"thunderx3t110", ThunderX3T110Model,
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// HiSilicon Processors.
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def : ProcessorModel<"tsv110", TSV110Model, ProcessorFeatures.TSV110,
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[TuneTSV110]>;
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-#ifdef ENABLE_AARCH64_HIP09
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// FIXME: HiSilicon HIP09 is currently modeled as a Cortex-A57.
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def : ProcessorModel<"hip09", CortexA57Model, ProcessorFeatures.HIP09,
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[TuneHIP09]>;
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-#endif
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// Support cyclone as an alias for apple-a7 so we can still LTO old bitcode.
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def : ProcessorModel<"cyclone", CycloneModel, ProcessorFeatures.AppleA7,
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diff --git a/llvm/lib/Target/AArch64/AArch64MacroFusion.cpp b/llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
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index 4963ec350db2..44daa06468c5 100644
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--- a/llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
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+++ b/llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
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@@ -51,12 +51,10 @@ static bool isArithmeticBccPair(const MachineInstr *FirstMI,
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case AArch64::SUBSXrr:
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case AArch64::BICSWrr:
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case AArch64::BICSXrr:
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-#if defined(ENABLE_AARCH64_HIP09)
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case AArch64::ADCSWr:
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case AArch64::ADCSXr:
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case AArch64::SBCSWr:
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case AArch64::SBCSXr:
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-#endif
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return true;
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case AArch64::ADDSWrs:
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case AArch64::ADDSXrs:
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@@ -189,7 +187,6 @@ static bool isLiteralsPair(const MachineInstr *FirstMI,
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SecondMI.getOperand(3).getImm() == 16))
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return true;
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-#if defined(ENABLE_AARCH64_HIP09)
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// 32 bit immediate.
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if ((FirstMI == nullptr || FirstMI->getOpcode() == AArch64::MOVNWi) &&
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(SecondMI.getOpcode() == AArch64::MOVKWi &&
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@@ -201,7 +198,6 @@ static bool isLiteralsPair(const MachineInstr *FirstMI,
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(SecondMI.getOpcode() == AArch64::MOVKWi &&
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SecondMI.getOperand(3).getImm() == 16))
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return true;
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-#endif
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// Upper half of 64 bit immediate.
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if ((FirstMI == nullptr ||
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@@ -457,7 +453,6 @@ static bool isAddSub2RegAndConstOnePair(const MachineInstr *FirstMI,
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return false;
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}
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-#if defined(ENABLE_AARCH64_HIP09)
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static bool isMvnClzPair(const MachineInstr *FirstMI,
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const MachineInstr &SecondMI) {
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// HIP09 supports fusion of MVN + CLZ.
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@@ -486,7 +481,6 @@ static bool isMvnClzPair(const MachineInstr *FirstMI,
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return false;
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}
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-#endif
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/// \brief Check if the instr pair, FirstMI and SecondMI, should be fused
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/// together. Given SecondMI, when FirstMI is unspecified, then check if
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@@ -523,10 +517,8 @@ static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
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if (ST.hasFuseAddSub2RegAndConstOne() &&
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isAddSub2RegAndConstOnePair(FirstMI, SecondMI))
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return true;
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-#if defined(ENABLE_AARCH64_HIP09)
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if (ST.hasFuseMvnClz() && isMvnClzPair(FirstMI, SecondMI))
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return true;
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-#endif
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return false;
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}
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diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
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index ddf22364c78e..1aff7e30a0cf 100644
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--- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
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+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
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@@ -266,7 +266,6 @@ void AArch64Subtarget::initializeProperties() {
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PrefFunctionAlignment = Align(16);
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PrefLoopAlignment = Align(4);
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break;
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-#if defined(ENABLE_AARCH64_HIP09)
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case HIP09:
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CacheLineSize = 64;
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PrefFunctionAlignment = Align(16);
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@@ -274,7 +273,6 @@ void AArch64Subtarget::initializeProperties() {
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VScaleForTuning = 2;
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DefaultSVETFOpts = TailFoldingOpts::Simple;
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break;
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-#endif
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case ThunderX3T110:
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CacheLineSize = 64;
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PrefFunctionAlignment = Align(16);
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diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h
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index 5f481f4f976a..8a1cebe96894 100644
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--- a/llvm/lib/Target/AArch64/AArch64Subtarget.h
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+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h
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@@ -88,9 +88,7 @@ public:
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ThunderXT88,
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ThunderX3T110,
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TSV110,
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-#if defined(ENABLE_AARCH64_HIP09)
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HIP09
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-#endif
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};
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protected:
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@@ -242,11 +240,7 @@ public:
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bool hasFusion() const {
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return hasArithmeticBccFusion() || hasArithmeticCbzFusion() ||
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hasFuseAES() || hasFuseArithmeticLogic() || hasFuseCCSelect() ||
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-#if defined(ENABLE_AARCH64_HIP09)
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hasFuseAdrpAdd() || hasFuseLiterals() || hasFuseMvnClz();
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-#else
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- hasFuseAdrpAdd() || hasFuseLiterals();
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-#endif
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}
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unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
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diff --git a/llvm/lib/Target/CMakeLists.txt b/llvm/lib/Target/CMakeLists.txt
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index 501ce1f2fe53..2739233f9ccb 100644
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--- a/llvm/lib/Target/CMakeLists.txt
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+++ b/llvm/lib/Target/CMakeLists.txt
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@@ -2,10 +2,6 @@ list(APPEND LLVM_COMMON_DEPENDS intrinsics_gen)
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list(APPEND LLVM_TABLEGEN_FLAGS -I ${LLVM_MAIN_SRC_DIR}/lib/Target)
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-if(LLVM_ENABLE_AARCH64_HIP09)
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- list(APPEND LLVM_TABLEGEN_FLAGS "-DENABLE_AARCH64_HIP09")
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-endif()
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-
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add_llvm_component_library(LLVMTarget
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Target.cpp
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TargetIntrinsicInfo.cpp
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diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp
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index 8b23be02edc0..8b1191a5b442 100644
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--- a/llvm/lib/TargetParser/Host.cpp
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+++ b/llvm/lib/TargetParser/Host.cpp
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@@ -257,9 +257,7 @@ StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) {
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// contents are specified in the various processor manuals.
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return StringSwitch<const char *>(Part)
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.Case("0xd01", "tsv110")
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-#if defined(ENABLE_AARCH64_HIP09)
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.Case("0xd02", "hip09")
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-#endif
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.Default("generic");
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if (Implementer == "0x51") // Qualcomm Technologies, Inc.
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diff --git a/llvm/test/CodeGen/AArch64/cpus-hip09.ll b/llvm/test/CodeGen/AArch64/cpus-hip09.ll
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deleted file mode 100644
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index dcf32e4dca89..000000000000
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--- a/llvm/test/CodeGen/AArch64/cpus-hip09.ll
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+++ /dev/null
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@@ -1,11 +0,0 @@
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-; REQUIRES: enable_enable_aarch64_hip09
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-; This tests that llc accepts all valid AArch64 CPUs
|
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-
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-; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=hip09 2>&1 | FileCheck %s
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-
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-; CHECK-NOT: {{.*}} is not a recognized processor for this target
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-; INVALID: {{.*}} is not a recognized processor for this target
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-
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-define i32 @f(i64 %z) {
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- ret i32 0
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-}
|
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diff --git a/llvm/test/CodeGen/AArch64/cpus.ll b/llvm/test/CodeGen/AArch64/cpus.ll
|
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index b24866064efa..56772f6c6049 100644
|
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--- a/llvm/test/CodeGen/AArch64/cpus.ll
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+++ b/llvm/test/CodeGen/AArch64/cpus.ll
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@@ -33,6 +33,7 @@
|
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; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=thunderx2t99 2>&1 | FileCheck %s
|
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; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=thunderx3t110 2>&1 | FileCheck %s
|
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; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=tsv110 2>&1 | FileCheck %s
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+; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=hip09 2>&1 | FileCheck %s
|
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; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=apple-latest 2>&1 | FileCheck %s
|
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; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=a64fx 2>&1 | FileCheck %s
|
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; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=ampere1 2>&1 | FileCheck %s
|
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diff --git a/llvm/test/CodeGen/AArch64/macro-fusion-mvnclz.mir b/llvm/test/CodeGen/AArch64/macro-fusion-mvnclz.mir
|
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index 64bf159370f9..26ba76ef0af5 100644
|
||||
--- a/llvm/test/CodeGen/AArch64/macro-fusion-mvnclz.mir
|
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+++ b/llvm/test/CodeGen/AArch64/macro-fusion-mvnclz.mir
|
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@@ -1,4 +1,3 @@
|
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-# REQUIRES: enable_enable_aarch64_hip09
|
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# RUN: llc -o - %s -mtriple=aarch64-- -mattr=+fuse-mvn-clz -run-pass postmisched | FileCheck %s --check-prefixes=CHECK,FUSION
|
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# RUN: llc -o - %s -mtriple=aarch64-- -mattr=-fuse-mvn-clz -run-pass postmisched | FileCheck %s --check-prefixes=CHECK,NOFUSION
|
||||
---
|
||||
diff --git a/llvm/test/CodeGen/AArch64/misched-fusion-lit-hip09.ll b/llvm/test/CodeGen/AArch64/misched-fusion-lit-hip09.ll
|
||||
deleted file mode 100644
|
||||
index d67fa5b4374c..000000000000
|
||||
--- a/llvm/test/CodeGen/AArch64/misched-fusion-lit-hip09.ll
|
||||
+++ /dev/null
|
||||
@@ -1,73 +0,0 @@
|
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-; REQUIRES: enable_enable_aarch64_hip09
|
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-; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=hip09 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSE-HIP09
|
||||
-
|
||||
-@g = common local_unnamed_addr global ptr null, align 8
|
||||
-
|
||||
-define dso_local ptr @litp(i32 %a, i32 %b) {
|
||||
-entry:
|
||||
- %add = add nsw i32 %b, %a
|
||||
- %idx.ext = sext i32 %add to i64
|
||||
- %add.ptr = getelementptr i8, ptr @litp, i64 %idx.ext
|
||||
- store ptr %add.ptr, ptr @g, align 8
|
||||
- ret ptr %add.ptr
|
||||
-
|
||||
-; CHECK-LABEL: litp:
|
||||
-; CHECK: adrp [[R:x[0-9]+]], litp
|
||||
-; CHECKFUSE-NEXT: add {{x[0-9]+}}, [[R]], :lo12:litp
|
||||
-}
|
||||
-
|
||||
-define dso_local ptr @litp_tune_generic(i32 %a, i32 %b) "tune-cpu"="generic" {
|
||||
-entry:
|
||||
- %add = add nsw i32 %b, %a
|
||||
- %idx.ext = sext i32 %add to i64
|
||||
- %add.ptr = getelementptr i8, ptr @litp_tune_generic, i64 %idx.ext
|
||||
- store ptr %add.ptr, ptr @g, align 8
|
||||
- ret ptr %add.ptr
|
||||
-
|
||||
-; CHECK-LABEL: litp_tune_generic:
|
||||
-; CHECK: adrp [[R:x[0-9]+]], litp_tune_generic
|
||||
-; CHECK-NEXT: add {{x[0-9]+}}, [[R]], :lo12:litp_tune_generic
|
||||
-}
|
||||
-
|
||||
-define dso_local i32 @liti(i32 %a, i32 %b) {
|
||||
-entry:
|
||||
- %add = add i32 %a, -262095121
|
||||
- %add1 = add i32 %add, %b
|
||||
- ret i32 %add1
|
||||
-
|
||||
-; CHECK-LABEL: liti:
|
||||
-; CHECK: mov [[R:w[0-9]+]], {{#[0-9]+}}
|
||||
-; CHECKDONT-NEXT: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
-; CHECKFUSE-NEXT: movk [[R]], {{#[0-9]+}}, lsl #16
|
||||
-; CHECKFUSE-HIP09: movk [[R]], {{#[0-9]+}}, lsl #16
|
||||
-}
|
||||
-
|
||||
-; Function Attrs: norecurse nounwind readnone
|
||||
-define dso_local i64 @litl(i64 %a, i64 %b) {
|
||||
-entry:
|
||||
- %add = add i64 %a, 2208998440489107183
|
||||
- %add1 = add i64 %add, %b
|
||||
- ret i64 %add1
|
||||
-
|
||||
-; CHECK-LABEL: litl:
|
||||
-; CHECK: mov [[R:x[0-9]+]], {{#[0-9]+}}
|
||||
-; CHECKDONT-NEXT: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
|
||||
-; CHECK-NEXT: movk [[R]], {{#[0-9]+}}, lsl #16
|
||||
-; CHECK: movk [[R]], {{#[0-9]+}}, lsl #32
|
||||
-; CHECK-NEXT: movk [[R]], {{#[0-9]+}}, lsl #48
|
||||
-}
|
||||
-
|
||||
-; Function Attrs: norecurse nounwind readnone
|
||||
-define dso_local double @litf() {
|
||||
-entry:
|
||||
- ret double 0x400921FB54442D18
|
||||
-
|
||||
-; CHECK-LABEL: litf:
|
||||
-; CHECK-DONT: adrp [[ADDR:x[0-9]+]], [[CSTLABEL:.LCP.*]]
|
||||
-; CHECK-DONT-NEXT: ldr {{d[0-9]+}}, {{[[]}}[[ADDR]], :lo12:[[CSTLABEL]]{{[]]}}
|
||||
-; CHECKFUSE-HIP09: mov [[R:x[0-9]+]], #11544
|
||||
-; CHECKFUSE-HIP09: movk [[R]], #21572, lsl #16
|
||||
-; CHECKFUSE-HIP09: movk [[R]], #8699, lsl #32
|
||||
-; CHECKFUSE-HIP09: movk [[R]], #16393, lsl #48
|
||||
-; CHECKFUSE-HIP09: fmov {{d[0-9]+}}, [[R]]
|
||||
-}
|
||||
diff --git a/llvm/test/CodeGen/AArch64/misched-fusion-lit.ll b/llvm/test/CodeGen/AArch64/misched-fusion-lit.ll
|
||||
index ad244d30df11..67cc7aa503b6 100644
|
||||
--- a/llvm/test/CodeGen/AArch64/misched-fusion-lit.ll
|
||||
+++ b/llvm/test/CodeGen/AArch64/misched-fusion-lit.ll
|
||||
@@ -7,6 +7,7 @@
|
||||
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m4 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSE
|
||||
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m5 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSE
|
||||
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=neoverse-n1 | FileCheck %s --check-prefix=CHECKFUSE-NEOVERSE
|
||||
+; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=hip09 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSE-HIP09
|
||||
|
||||
@g = common local_unnamed_addr global ptr null, align 8
|
||||
|
||||
@@ -59,6 +60,7 @@ entry:
|
||||
; CHECK: mov [[R:w[0-9]+]], {{#[0-9]+}}
|
||||
; CHECKDONT-NEXT: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
|
||||
; CHECKFUSE-NEXT: movk [[R]], {{#[0-9]+}}, lsl #16
|
||||
+; CHECKFUSE-HIP09: movk [[R]], {{#[0-9]+}}, lsl #16
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
@@ -89,4 +91,9 @@ entry:
|
||||
; CHECK-FUSE: movk [[R]], #8699, lsl #32
|
||||
; CHECK-FUSE: movk [[R]], #16393, lsl #48
|
||||
; CHECK-FUSE: fmov {{d[0-9]+}}, [[R]]
|
||||
+; CHECKFUSE-HIP09: mov [[R:x[0-9]+]], #11544
|
||||
+; CHECKFUSE-HIP09: movk [[R]], #21572, lsl #16
|
||||
+; CHECKFUSE-HIP09: movk [[R]], #8699, lsl #32
|
||||
+; CHECKFUSE-HIP09: movk [[R]], #16393, lsl #48
|
||||
+; CHECKFUSE-HIP09: fmov {{d[0-9]+}}, [[R]]
|
||||
}
|
||||
diff --git a/llvm/test/CodeGen/AArch64/remat-hip09.ll b/llvm/test/CodeGen/AArch64/remat-hip09.ll
|
||||
deleted file mode 100644
|
||||
index aec0d18ae73f..000000000000
|
||||
--- a/llvm/test/CodeGen/AArch64/remat-hip09.ll
|
||||
+++ /dev/null
|
||||
@@ -1,18 +0,0 @@
|
||||
-; REQUIRES: enable_enable_aarch64_hip09
|
||||
-; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=hip09 -o - %s | FileCheck %s
|
||||
-
|
||||
-%X = type { i64, i64, i64 }
|
||||
-declare void @f(ptr)
|
||||
-define void @t() {
|
||||
-entry:
|
||||
- %tmp = alloca %X
|
||||
- call void @f(ptr %tmp)
|
||||
-; CHECK: add x0, sp, #8
|
||||
-; CHECK-NOT: mov
|
||||
-; CHECK-NEXT: bl f
|
||||
- call void @f(ptr %tmp)
|
||||
-; CHECK: add x0, sp, #8
|
||||
-; CHECK-NOT: mov
|
||||
-; CHECK-NEXT: bl f
|
||||
- ret void
|
||||
-}
|
||||
diff --git a/llvm/test/CodeGen/AArch64/remat.ll b/llvm/test/CodeGen/AArch64/remat.ll
|
||||
index 483c4d71ee21..fa039246c7f5 100644
|
||||
--- a/llvm/test/CodeGen/AArch64/remat.ll
|
||||
+++ b/llvm/test/CodeGen/AArch64/remat.ll
|
||||
@@ -22,6 +22,7 @@
|
||||
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=kryo -o - %s | FileCheck %s
|
||||
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx2t99 -o - %s | FileCheck %s
|
||||
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=tsv110 -o - %s | FileCheck %s
|
||||
+; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=hip09 -o - %s | FileCheck %s
|
||||
; RUN: llc -mtriple=aarch64-linux-gnuabi -mattr=+custom-cheap-as-move -o - %s | FileCheck %s
|
||||
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx3t110 -o - %s | FileCheck %s
|
||||
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=ampere1 -o - %s | FileCheck %s
|
||||
diff --git a/llvm/test/lit.site.cfg.py.in b/llvm/test/lit.site.cfg.py.in
|
||||
index 6145a514f008..20c1ecca1d43 100644
|
||||
--- a/llvm/test/lit.site.cfg.py.in
|
||||
+++ b/llvm/test/lit.site.cfg.py.in
|
||||
@@ -63,14 +63,10 @@ config.dxil_tests = @LLVM_INCLUDE_DXIL_TESTS@
|
||||
config.have_llvm_driver = @LLVM_TOOL_LLVM_DRIVER_BUILD@
|
||||
config.use_classic_flang = @LLVM_ENABLE_CLASSIC_FLANG@
|
||||
config.enable_enable_autotuner = @LLVM_ENABLE_AUTOTUNER@
|
||||
-config.enable_enable_aarch64_hip09 = @LLVM_ENABLE_AARCH64_HIP09@
|
||||
|
||||
import lit.llvm
|
||||
lit.llvm.initialize(lit_config, config)
|
||||
|
||||
-if config.enable_enable_aarch64_hip09:
|
||||
- config.available_features.add("enable_enable_aarch64_hip09")
|
||||
-
|
||||
# Let the main config do the real work.
|
||||
lit_config.load_config(
|
||||
config, os.path.join(config.llvm_src_root, "test/lit.cfg.py"))
|
||||
diff --git a/llvm/unittests/TargetParser/Host.cpp b/llvm/unittests/TargetParser/Host.cpp
|
||||
index 4b4c81514896..cfc41486b173 100644
|
||||
--- a/llvm/unittests/TargetParser/Host.cpp
|
||||
+++ b/llvm/unittests/TargetParser/Host.cpp
|
||||
@@ -250,11 +250,9 @@ CPU part : 0x0a1
|
||||
EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x48\n"
|
||||
"CPU part : 0xd01"),
|
||||
"tsv110");
|
||||
-#if defined(ENABLE_AARCH64_HIP09)
|
||||
EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x48\n"
|
||||
"CPU part : 0xd02"),
|
||||
"hip09");
|
||||
-#endif
|
||||
|
||||
// Verify A64FX.
|
||||
const std::string A64FXProcCpuInfo = R"(
|
||||
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
|
||||
index 94e0047e567b..daa38474004e 100644
|
||||
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
|
||||
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
|
||||
@@ -1421,7 +1421,6 @@ INSTANTIATE_TEST_SUITE_P(
|
||||
AArch64::AEK_PROFILE | AArch64::AEK_FP16 |
|
||||
AArch64::AEK_FP16FML | AArch64::AEK_DOTPROD,
|
||||
"8.2-A"),
|
||||
-#if defined(ENABLE_AARCH64_HIP09)
|
||||
ARMCPUTestParams(
|
||||
"hip09", "armv8.5-a", "crypto-neon-fp-armv8",
|
||||
AArch64::AEK_CRC | AArch64::AEK_FP | AArch64::AEK_SIMD |
|
||||
@@ -1432,7 +1431,6 @@ INSTANTIATE_TEST_SUITE_P(
|
||||
AArch64::AEK_FP16FML | AArch64::AEK_SVE | AArch64::AEK_I8MM |
|
||||
AArch64::AEK_F32MM | AArch64::AEK_F64MM | AArch64::AEK_BF16,
|
||||
"8.5-A"),
|
||||
-#endif
|
||||
ARMCPUTestParams("a64fx", "armv8.2-a", "crypto-neon-fp-armv8",
|
||||
AArch64::AEK_CRC | AArch64::AEK_AES |
|
||||
AArch64::AEK_SHA2 | AArch64::AEK_FP |
|
||||
@@ -1449,11 +1447,7 @@ INSTANTIATE_TEST_SUITE_P(
|
||||
"8.2-A")));
|
||||
|
||||
// Note: number of CPUs includes aliases.
|
||||
-#if defined(ENABLE_AARCH64_HIP09)
|
||||
static constexpr unsigned NumAArch64CPUArchs = 63;
|
||||
-#else
|
||||
-static constexpr unsigned NumAArch64CPUArchs = 62;
|
||||
-#endif
|
||||
|
||||
TEST(TargetParserTest, testAArch64CPUArchList) {
|
||||
SmallVector<StringRef, NumAArch64CPUArchs> List;
|
||||
--
|
||||
2.43.0
|
||||
|
||||
@ -0,0 +1,72 @@
|
||||
From 28e3fc80336935bc8bed372e78616ef5be9f4908 Mon Sep 17 00:00:00 2001
|
||||
From: Arthur Eubanks <aeubanks@google.com>
|
||||
Date: Thu, 27 Jul 2023 13:27:58 -0700
|
||||
Subject: [PATCH] Don't zero out noreg operands
|
||||
|
||||
A tail call may have $noreg operands.
|
||||
|
||||
Fixes a crash.
|
||||
|
||||
Reviewed By: xgupta
|
||||
|
||||
Differential Revision: https://reviews.llvm.org/D156485
|
||||
---
|
||||
llvm/lib/CodeGen/PrologEpilogInserter.cpp | 9 +++++++--
|
||||
llvm/test/CodeGen/X86/zero-call-used-regs.ll | 14 ++++++++++++++
|
||||
2 files changed, 21 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
|
||||
index e323aaaeefaf..49047719fdaa 100644
|
||||
--- a/llvm/lib/CodeGen/PrologEpilogInserter.cpp
|
||||
+++ b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
|
||||
@@ -1285,6 +1285,8 @@ void PEI::insertZeroCallUsedRegs(MachineFunction &MF) {
|
||||
continue;
|
||||
|
||||
MCRegister Reg = MO.getReg();
|
||||
+ if (!Reg)
|
||||
+ continue;
|
||||
|
||||
// This picks up sibling registers (e.q. %al -> %ah).
|
||||
for (MCRegUnit Unit : TRI.regunits(Reg))
|
||||
@@ -1308,8 +1310,11 @@ void PEI::insertZeroCallUsedRegs(MachineFunction &MF) {
|
||||
if (!MO.isReg())
|
||||
continue;
|
||||
|
||||
- for (const MCPhysReg &Reg :
|
||||
- TRI.sub_and_superregs_inclusive(MO.getReg()))
|
||||
+ MCRegister Reg = MO.getReg();
|
||||
+ if (!Reg)
|
||||
+ continue;
|
||||
+
|
||||
+ for (const MCPhysReg Reg : TRI.sub_and_superregs_inclusive(Reg))
|
||||
RegsToZero.reset(Reg);
|
||||
}
|
||||
}
|
||||
diff --git a/llvm/test/CodeGen/X86/zero-call-used-regs.ll b/llvm/test/CodeGen/X86/zero-call-used-regs.ll
|
||||
index 63d51c916bb9..97ad5ce9c8cb 100644
|
||||
--- a/llvm/test/CodeGen/X86/zero-call-used-regs.ll
|
||||
+++ b/llvm/test/CodeGen/X86/zero-call-used-regs.ll
|
||||
@@ -241,6 +241,20 @@ entry:
|
||||
ret i32 %x
|
||||
}
|
||||
|
||||
+define dso_local void @tailcall(ptr %p) local_unnamed_addr #0 "zero-call-used-regs"="used-gpr" {
|
||||
+; I386-LABEL: tailcall:
|
||||
+; I386: # %bb.0:
|
||||
+; I386-NEXT: movl {{[0-9]+}}(%esp), %eax
|
||||
+; I386-NEXT: jmpl *(%eax) # TAILCALL
|
||||
+;
|
||||
+; X86-64-LABEL: tailcall:
|
||||
+; X86-64: # %bb.0:
|
||||
+; X86-64-NEXT: jmpq *(%rdi) # TAILCALL
|
||||
+ %c = load ptr, ptr %p
|
||||
+ tail call void %c()
|
||||
+ ret void
|
||||
+}
|
||||
+
|
||||
; Don't emit zeroing registers in "main" function.
|
||||
define dso_local i32 @main() local_unnamed_addr #1 {
|
||||
; I386-LABEL: main:
|
||||
--
|
||||
2.43.0
|
||||
|
||||
10
llvm.spec
10
llvm.spec
@ -46,7 +46,7 @@
|
||||
|
||||
Name: %{pkg_name}
|
||||
Version: %{maj_ver}.%{min_ver}.%{patch_ver}
|
||||
Release: 22
|
||||
Release: 24
|
||||
Summary: The Low Level Virtual Machine
|
||||
|
||||
License: NCSA
|
||||
@ -83,6 +83,8 @@ Patch23: 0023-AArch64-Support-HiSilicon-s-HIP09-Processor.patch
|
||||
Patch24: 0024-Backport-LoongArch-fix-and-add-some-new-support.patch
|
||||
Patch25: 0025-Backport-Simple-check-to-ignore-Inline-asm-fwait-insertion.patch
|
||||
Patch26: 0026-Add-arch-restriction-for-BiSheng-Autotuner.patch
|
||||
Patch27: 0027-AArch64-Delete-hip09-macro.patch
|
||||
Patch28: 0028-backport-Clang-Fix-crash-with-fzero-call-used-regs.patch
|
||||
|
||||
BuildRequires: binutils-devel
|
||||
BuildRequires: cmake
|
||||
@ -376,6 +378,12 @@ LD_LIBRARY_PATH=%{buildroot}/%{install_libdir} %{__ninja} check-all -C %{__cmake
|
||||
%{install_includedir}/llvm-gmock
|
||||
|
||||
%changelog
|
||||
* Tue Nov 19 2024 xiajingze <xiajingze1@huawei.com> - 17.0.6-24
|
||||
- [backport][Clang] Fix crash with -fzero-call-used-regs
|
||||
|
||||
* Mon Nov 18 2024 xiajingze <xiajingze1@huawei.com> - 17.0.6-23
|
||||
- [AArch64] Delete hip09 macro
|
||||
|
||||
* Mon Nov 18 2024 liyunfei <liyunfei33@huawei.net> - 17.0.6-22
|
||||
- Add arch restriction for BiSheng Autotuner
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user