365 lines
16 KiB
Diff
365 lines
16 KiB
Diff
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From f2495d7efb79fdc82af6147f7201d9cf3c91beba Mon Sep 17 00:00:00 2001
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From: Jinyang He <hejinyang@loongson.cn>
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Date: Wed, 27 Dec 2023 08:51:48 +0800
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Subject: [PATCH 04/14] [LoongArch] Emit R_LARCH_RELAX when expanding some
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LoadAddress (#72961)
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Emit relax relocs when expand non-large la.pcrel and non-large la.got on
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llvm-mc stage, which like what does on GAS.
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1, la.pcrel -> PCALA_HI20 + RELAX + PCALA_LO12 + RELAX
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2, la.got -> GOT_PC_HI20 + RELAX + GOT_PC_LO12 + RELAX
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(cherry picked from commit b3ef8dce9811b2725639b0d4fac3f85c7e112817)
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Change-Id: I222daf60b36ee70e23c76b753e1d2a3b8148f44b
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---
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.../AsmParser/LoongArchAsmParser.cpp | 12 +--
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.../MCTargetDesc/LoongArchMCCodeEmitter.cpp | 13 +++
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.../MCTargetDesc/LoongArchMCExpr.cpp | 7 +-
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.../LoongArch/MCTargetDesc/LoongArchMCExpr.h | 8 +-
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llvm/test/MC/LoongArch/Macros/macros-la.s | 84 ++++++++++++++++---
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llvm/test/MC/LoongArch/Misc/subsection.s | 2 +-
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.../MC/LoongArch/Relocations/relax-addsub.s | 16 +++-
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7 files changed, 115 insertions(+), 27 deletions(-)
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diff --git a/llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp b/llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
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index 94d530306536..a132e645c864 100644
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--- a/llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
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+++ b/llvm/lib/Target/LoongArch/AsmParser/LoongArchAsmParser.cpp
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@@ -86,7 +86,7 @@ class LoongArchAsmParser : public MCTargetAsmParser {
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// "emitLoadAddress*" functions.
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void emitLAInstSeq(MCRegister DestReg, MCRegister TmpReg,
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const MCExpr *Symbol, SmallVectorImpl<Inst> &Insts,
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- SMLoc IDLoc, MCStreamer &Out);
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+ SMLoc IDLoc, MCStreamer &Out, bool RelaxHint = false);
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// Helper to emit pseudo instruction "la.abs $rd, sym".
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void emitLoadAddressAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
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@@ -749,12 +749,14 @@ bool LoongArchAsmParser::ParseInstruction(ParseInstructionInfo &Info,
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void LoongArchAsmParser::emitLAInstSeq(MCRegister DestReg, MCRegister TmpReg,
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const MCExpr *Symbol,
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SmallVectorImpl<Inst> &Insts,
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- SMLoc IDLoc, MCStreamer &Out) {
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+ SMLoc IDLoc, MCStreamer &Out,
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+ bool RelaxHint) {
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MCContext &Ctx = getContext();
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for (LoongArchAsmParser::Inst &Inst : Insts) {
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unsigned Opc = Inst.Opc;
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LoongArchMCExpr::VariantKind VK = Inst.VK;
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- const LoongArchMCExpr *LE = LoongArchMCExpr::create(Symbol, VK, Ctx);
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+ const LoongArchMCExpr *LE =
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+ LoongArchMCExpr::create(Symbol, VK, Ctx, RelaxHint);
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switch (Opc) {
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default:
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llvm_unreachable("unexpected opcode");
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@@ -855,7 +857,7 @@ void LoongArchAsmParser::emitLoadAddressPcrel(MCInst &Inst, SMLoc IDLoc,
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Insts.push_back(
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LoongArchAsmParser::Inst(ADDI, LoongArchMCExpr::VK_LoongArch_PCALA_LO12));
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- emitLAInstSeq(DestReg, DestReg, Symbol, Insts, IDLoc, Out);
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+ emitLAInstSeq(DestReg, DestReg, Symbol, Insts, IDLoc, Out, true);
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}
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void LoongArchAsmParser::emitLoadAddressPcrelLarge(MCInst &Inst, SMLoc IDLoc,
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@@ -901,7 +903,7 @@ void LoongArchAsmParser::emitLoadAddressGot(MCInst &Inst, SMLoc IDLoc,
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Insts.push_back(
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LoongArchAsmParser::Inst(LD, LoongArchMCExpr::VK_LoongArch_GOT_PC_LO12));
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- emitLAInstSeq(DestReg, DestReg, Symbol, Insts, IDLoc, Out);
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+ emitLAInstSeq(DestReg, DestReg, Symbol, Insts, IDLoc, Out, true);
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}
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void LoongArchAsmParser::emitLoadAddressGotLarge(MCInst &Inst, SMLoc IDLoc,
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diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp
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index 03fb9e008ae9..08c0820cb862 100644
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--- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp
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+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCCodeEmitter.cpp
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@@ -19,6 +19,7 @@
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#include "llvm/MC/MCInstBuilder.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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+#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/EndianStream.h"
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@@ -120,12 +121,15 @@ LoongArchMCCodeEmitter::getExprOpValue(const MCInst &MI, const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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assert(MO.isExpr() && "getExprOpValue expects only expressions");
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+ bool RelaxCandidate = false;
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+ bool EnableRelax = STI.hasFeature(LoongArch::FeatureRelax);
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const MCExpr *Expr = MO.getExpr();
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MCExpr::ExprKind Kind = Expr->getKind();
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LoongArch::Fixups FixupKind = LoongArch::fixup_loongarch_invalid;
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if (Kind == MCExpr::Target) {
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const LoongArchMCExpr *LAExpr = cast<LoongArchMCExpr>(Expr);
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+ RelaxCandidate = LAExpr->getRelaxHint();
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switch (LAExpr->getKind()) {
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case LoongArchMCExpr::VK_LoongArch_None:
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case LoongArchMCExpr::VK_LoongArch_Invalid:
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@@ -269,6 +273,15 @@ LoongArchMCCodeEmitter::getExprOpValue(const MCInst &MI, const MCOperand &MO,
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Fixups.push_back(
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MCFixup::create(0, Expr, MCFixupKind(FixupKind), MI.getLoc()));
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+
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+ // Emit an R_LARCH_RELAX if linker relaxation is enabled and LAExpr has relax
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+ // hint.
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+ if (EnableRelax && RelaxCandidate) {
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+ const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx);
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+ Fixups.push_back(MCFixup::create(
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+ 0, Dummy, MCFixupKind(LoongArch::fixup_loongarch_relax), MI.getLoc()));
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+ }
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+
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return 0;
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}
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diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCExpr.cpp b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCExpr.cpp
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index 993111552a31..82c992b1cc8c 100644
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--- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCExpr.cpp
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+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCExpr.cpp
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@@ -25,9 +25,10 @@ using namespace llvm;
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#define DEBUG_TYPE "loongarch-mcexpr"
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-const LoongArchMCExpr *
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-LoongArchMCExpr::create(const MCExpr *Expr, VariantKind Kind, MCContext &Ctx) {
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- return new (Ctx) LoongArchMCExpr(Expr, Kind);
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+const LoongArchMCExpr *LoongArchMCExpr::create(const MCExpr *Expr,
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+ VariantKind Kind, MCContext &Ctx,
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+ bool Hint) {
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+ return new (Ctx) LoongArchMCExpr(Expr, Kind, Hint);
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}
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void LoongArchMCExpr::printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const {
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diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCExpr.h b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCExpr.h
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index 0945cf82db86..93251f824103 100644
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--- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCExpr.h
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+++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCExpr.h
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@@ -67,16 +67,18 @@ public:
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private:
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const MCExpr *Expr;
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const VariantKind Kind;
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+ const bool RelaxHint;
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- explicit LoongArchMCExpr(const MCExpr *Expr, VariantKind Kind)
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- : Expr(Expr), Kind(Kind) {}
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+ explicit LoongArchMCExpr(const MCExpr *Expr, VariantKind Kind, bool Hint)
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+ : Expr(Expr), Kind(Kind), RelaxHint(Hint) {}
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public:
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static const LoongArchMCExpr *create(const MCExpr *Expr, VariantKind Kind,
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- MCContext &Ctx);
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+ MCContext &Ctx, bool Hint = false);
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VariantKind getKind() const { return Kind; }
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const MCExpr *getSubExpr() const { return Expr; }
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+ bool getRelaxHint() const { return RelaxHint; }
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void printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const override;
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bool evaluateAsRelocatableImpl(MCValue &Res, const MCAsmLayout *Layout,
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diff --git a/llvm/test/MC/LoongArch/Macros/macros-la.s b/llvm/test/MC/LoongArch/Macros/macros-la.s
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index 924e4326b8e5..1a1d12d7d7df 100644
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--- a/llvm/test/MC/LoongArch/Macros/macros-la.s
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+++ b/llvm/test/MC/LoongArch/Macros/macros-la.s
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@@ -1,66 +1,128 @@
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# RUN: llvm-mc --triple=loongarch64 %s | FileCheck %s
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+# RUN: llvm-mc --filetype=obj --triple=loongarch64 --mattr=-relax %s -o %t
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+# RUN: llvm-readobj -r %t | FileCheck %s --check-prefix=RELOC
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+# RUN: llvm-mc --filetype=obj --triple=loongarch64 --mattr=+relax %s -o %t.relax
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+# RUN: llvm-readobj -r %t.relax | FileCheck %s --check-prefixes=RELOC,RELAX
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+
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+# RELOC: Relocations [
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+# RELOC-NEXT: Section ({{.*}}) .rela.text {
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la.abs $a0, sym_abs
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# CHECK: lu12i.w $a0, %abs_hi20(sym_abs)
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# CHECK-NEXT: ori $a0, $a0, %abs_lo12(sym_abs)
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# CHECK-NEXT: lu32i.d $a0, %abs64_lo20(sym_abs)
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# CHECK-NEXT: lu52i.d $a0, $a0, %abs64_hi12(sym_abs)
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+# CHECK-EMPTY:
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+# RELOC-NEXT: R_LARCH_ABS_HI20 sym_abs 0x0
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+# RELOC-NEXT: R_LARCH_ABS_LO12 sym_abs 0x0
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+# RELOC-NEXT: R_LARCH_ABS64_LO20 sym_abs 0x0
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+# RELOC-NEXT: R_LARCH_ABS64_HI12 sym_abs 0x0
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la.pcrel $a0, sym_pcrel
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-# CHECK: pcalau12i $a0, %pc_hi20(sym_pcrel)
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+# CHECK-NEXT: pcalau12i $a0, %pc_hi20(sym_pcrel)
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# CHECK-NEXT: addi.d $a0, $a0, %pc_lo12(sym_pcrel)
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+# CHECK-EMPTY:
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+# RELOC-NEXT: R_LARCH_PCALA_HI20 sym_pcrel 0x0
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+# RELAX-NEXT: R_LARCH_RELAX - 0x0
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+# RELOC-NEXT: R_LARCH_PCALA_LO12 sym_pcrel 0x0
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+# RELAX-NEXT: R_LARCH_RELAX - 0x0
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la.pcrel $a0, $a1, sym_pcrel_large
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-# CHECK: pcalau12i $a0, %pc_hi20(sym_pcrel_large)
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+# CHECK-NEXT: pcalau12i $a0, %pc_hi20(sym_pcrel_large)
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# CHECK-NEXT: addi.d $a1, $zero, %pc_lo12(sym_pcrel_large)
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# CHECK-NEXT: lu32i.d $a1, %pc64_lo20(sym_pcrel_large)
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# CHECK-NEXT: lu52i.d $a1, $a1, %pc64_hi12(sym_pcrel_large)
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# CHECK-NEXT: add.d $a0, $a0, $a1
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+# CHECK-EMPTY:
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+# RELOC-NEXT: R_LARCH_PCALA_HI20 sym_pcrel_large 0x0
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+# RELOC-NEXT: R_LARCH_PCALA_LO12 sym_pcrel_large 0x0
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+# RELOC-NEXT: R_LARCH_PCALA64_LO20 sym_pcrel_large 0x0
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+# RELOC-NEXT: R_LARCH_PCALA64_HI12 sym_pcrel_large 0x0
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la.got $a0, sym_got
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-# CHECK: pcalau12i $a0, %got_pc_hi20(sym_got)
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+# CHECK-NEXT: pcalau12i $a0, %got_pc_hi20(sym_got)
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# CHECK-NEXT: ld.d $a0, $a0, %got_pc_lo12(sym_got)
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+# CHECK-EMPTY:
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+# RELOC-NEXT: R_LARCH_GOT_PC_HI20 sym_got 0x0
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+# RELAX-NEXT: R_LARCH_RELAX - 0x0
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+# RELOC-NEXT: R_LARCH_GOT_PC_LO12 sym_got 0x0
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+# RELAX-NEXT: R_LARCH_RELAX - 0x0
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la.got $a0, $a1, sym_got_large
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-# CHECK: pcalau12i $a0, %got_pc_hi20(sym_got_large)
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+# CHECK-NEXT: pcalau12i $a0, %got_pc_hi20(sym_got_large)
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# CHECK-NEXT: addi.d $a1, $zero, %got_pc_lo12(sym_got_large)
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# CHECK-NEXT: lu32i.d $a1, %got64_pc_lo20(sym_got_large)
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# CHECK-NEXT: lu52i.d $a1, $a1, %got64_pc_hi12(sym_got_large)
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# CHECK-NEXT: ldx.d $a0, $a0, $a1
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+# CHECK-EMPTY:
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+# RELOC-NEXT: R_LARCH_GOT_PC_HI20 sym_got_large 0x0
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+# RELOC-NEXT: R_LARCH_GOT_PC_LO12 sym_got_large 0x0
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+# RELOC-NEXT: R_LARCH_GOT64_PC_LO20 sym_got_large 0x0
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+# RELOC-NEXT: R_LARCH_GOT64_PC_HI12 sym_got_large 0x0
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la.tls.le $a0, sym_le
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-# CHECK: lu12i.w $a0, %le_hi20(sym_le)
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+# CHECK-NEXT: lu12i.w $a0, %le_hi20(sym_le)
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# CHECK-NEXT: ori $a0, $a0, %le_lo12(sym_le)
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+# CHECK-EMPTY:
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+# RELOC-NEXT: R_LARCH_TLS_LE_HI20 sym_le 0x0
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+# RELOC-NEXT: R_LARCH_TLS_LE_LO12 sym_le 0x0
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la.tls.ie $a0, sym_ie
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-# CHECK: pcalau12i $a0, %ie_pc_hi20(sym_ie)
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+# CHECK-NEXT: pcalau12i $a0, %ie_pc_hi20(sym_ie)
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# CHECK-NEXT: ld.d $a0, $a0, %ie_pc_lo12(sym_ie)
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+# CHECK-EMPTY:
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+# RELOC-NEXT: R_LARCH_TLS_IE_PC_HI20 sym_ie 0x0
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+# RELOC-NEXT: R_LARCH_TLS_IE_PC_LO12 sym_ie 0x0
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la.tls.ie $a0, $a1, sym_ie_large
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-# CHECK: pcalau12i $a0, %ie_pc_hi20(sym_ie_large)
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+# CHECK-NEXT: pcalau12i $a0, %ie_pc_hi20(sym_ie_large)
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# CHECK-NEXT: addi.d $a1, $zero, %ie_pc_lo12(sym_ie_large)
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# CHECK-NEXT: lu32i.d $a1, %ie64_pc_lo20(sym_ie_large)
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# CHECK-NEXT: lu52i.d $a1, $a1, %ie64_pc_hi12(sym_ie_large)
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# CHECK-NEXT: ldx.d $a0, $a0, $a1
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+# CHECK-EMPTY:
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+# RELOC-NEXT: R_LARCH_TLS_IE_PC_HI20 sym_ie_large 0x0
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+# RELOC-NEXT: R_LARCH_TLS_IE_PC_LO12 sym_ie_large 0x0
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+# RELOC-NEXT: R_LARCH_TLS_IE64_PC_LO20 sym_ie_large 0x0
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+# RELOC-NEXT: R_LARCH_TLS_IE64_PC_HI12 sym_ie_large 0x0
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la.tls.ld $a0, sym_ld
|
||
|
|
-# CHECK: pcalau12i $a0, %ld_pc_hi20(sym_ld)
|
||
|
|
+# CHECK-NEXT: pcalau12i $a0, %ld_pc_hi20(sym_ld)
|
||
|
|
# CHECK-NEXT: addi.d $a0, $a0, %got_pc_lo12(sym_ld)
|
||
|
|
+# CHECK-EMPTY:
|
||
|
|
+# RELOC-NEXT: R_LARCH_TLS_LD_PC_HI20 sym_ld 0x0
|
||
|
|
+# RELOC-NEXT: R_LARCH_GOT_PC_LO12 sym_ld 0x0
|
||
|
|
|
||
|
|
la.tls.ld $a0, $a1, sym_ld_large
|
||
|
|
-# CHECK: pcalau12i $a0, %ld_pc_hi20(sym_ld_large)
|
||
|
|
+# CHECK-NEXT: pcalau12i $a0, %ld_pc_hi20(sym_ld_large)
|
||
|
|
# CHECK-NEXT: addi.d $a1, $zero, %got_pc_lo12(sym_ld_large)
|
||
|
|
# CHECK-NEXT: lu32i.d $a1, %got64_pc_lo20(sym_ld_large)
|
||
|
|
# CHECK-NEXT: lu52i.d $a1, $a1, %got64_pc_hi12(sym_ld_large)
|
||
|
|
# CHECK-NEXT: add.d $a0, $a0, $a1
|
||
|
|
+# CHECK-EMPTY:
|
||
|
|
+# RELOC-NEXT: R_LARCH_TLS_LD_PC_HI20 sym_ld_large 0x0
|
||
|
|
+# RELOC-NEXT: R_LARCH_GOT_PC_LO12 sym_ld_large 0x0
|
||
|
|
+# RELOC-NEXT: R_LARCH_GOT64_PC_LO20 sym_ld_large 0x0
|
||
|
|
+# RELOC-NEXT: R_LARCH_GOT64_PC_HI12 sym_ld_large 0x0
|
||
|
|
|
||
|
|
la.tls.gd $a0, sym_gd
|
||
|
|
-# CHECK: pcalau12i $a0, %gd_pc_hi20(sym_gd)
|
||
|
|
+# CHECK-NEXT: pcalau12i $a0, %gd_pc_hi20(sym_gd)
|
||
|
|
# CHECK-NEXT: addi.d $a0, $a0, %got_pc_lo12(sym_gd)
|
||
|
|
+# CHECK-EMPTY:
|
||
|
|
+# RELOC-NEXT: R_LARCH_TLS_GD_PC_HI20 sym_gd 0x0
|
||
|
|
+# RELOC-NEXT: R_LARCH_GOT_PC_LO12 sym_gd 0x0
|
||
|
|
|
||
|
|
la.tls.gd $a0, $a1, sym_gd_large
|
||
|
|
-# CHECK: pcalau12i $a0, %gd_pc_hi20(sym_gd_large)
|
||
|
|
+# CHECK-NEXT: pcalau12i $a0, %gd_pc_hi20(sym_gd_large)
|
||
|
|
# CHECK-NEXT: addi.d $a1, $zero, %got_pc_lo12(sym_gd_large)
|
||
|
|
# CHECK-NEXT: lu32i.d $a1, %got64_pc_lo20(sym_gd_large)
|
||
|
|
# CHECK-NEXT: lu52i.d $a1, $a1, %got64_pc_hi12(sym_gd_large)
|
||
|
|
# CHECK-NEXT: add.d $a0, $a0, $a1
|
||
|
|
+# CHECK-EMPTY:
|
||
|
|
+# RELOC-NEXT: R_LARCH_TLS_GD_PC_HI20 sym_gd_large 0x0
|
||
|
|
+# RELOC-NEXT: R_LARCH_GOT_PC_LO12 sym_gd_large 0x0
|
||
|
|
+# RELOC-NEXT: R_LARCH_GOT64_PC_LO20 sym_gd_large 0x0
|
||
|
|
+# RELOC-NEXT: R_LARCH_GOT64_PC_HI12 sym_gd_large 0x0
|
||
|
|
+
|
||
|
|
+# RELOC-NEXT: }
|
||
|
|
+# RELOC-NEXT: ]
|
||
|
|
diff --git a/llvm/test/MC/LoongArch/Misc/subsection.s b/llvm/test/MC/LoongArch/Misc/subsection.s
|
||
|
|
index 0bd22b474536..566a2408d691 100644
|
||
|
|
--- a/llvm/test/MC/LoongArch/Misc/subsection.s
|
||
|
|
+++ b/llvm/test/MC/LoongArch/Misc/subsection.s
|
||
|
|
@@ -1,5 +1,5 @@
|
||
|
|
# RUN: not llvm-mc --filetype=obj --triple=loongarch64 --mattr=-relax %s -o /dev/null 2>&1 | FileCheck %s --check-prefixes=ERR,NORELAX --implicit-check-not=error:
|
||
|
|
-## TODO: not llvm-mc --filetype=obj --triple=loongarch64 --mattr=+relax %s -o /dev/null 2>&1 | FileCheck %s --check-prefixes=ERR,RELAX --implicit-check-not=error:
|
||
|
|
+# RUN: not llvm-mc --filetype=obj --triple=loongarch64 --mattr=+relax %s -o /dev/null 2>&1 | FileCheck %s --check-prefixes=ERR,RELAX --implicit-check-not=error:
|
||
|
|
|
||
|
|
a:
|
||
|
|
nop
|
||
|
|
diff --git a/llvm/test/MC/LoongArch/Relocations/relax-addsub.s b/llvm/test/MC/LoongArch/Relocations/relax-addsub.s
|
||
|
|
index 532eb4e0561a..c4454f5bb98d 100644
|
||
|
|
--- a/llvm/test/MC/LoongArch/Relocations/relax-addsub.s
|
||
|
|
+++ b/llvm/test/MC/LoongArch/Relocations/relax-addsub.s
|
||
|
|
@@ -18,7 +18,9 @@
|
||
|
|
# RELAX: Relocations [
|
||
|
|
# RELAX-NEXT: Section ({{.*}}) .rela.text {
|
||
|
|
# RELAX-NEXT: 0x10 R_LARCH_PCALA_HI20 .L1 0x0
|
||
|
|
+# RELAX-NEXT: 0x10 R_LARCH_RELAX - 0x0
|
||
|
|
# RELAX-NEXT: 0x14 R_LARCH_PCALA_LO12 .L1 0x0
|
||
|
|
+# RELAX-NEXT: 0x14 R_LARCH_RELAX - 0x0
|
||
|
|
# RELAX-NEXT: }
|
||
|
|
# RELAX-NEXT: Section ({{.*}}) .rela.data {
|
||
|
|
# RELAX-NEXT: 0xF R_LARCH_ADD8 .L3 0x0
|
||
|
|
@@ -29,13 +31,21 @@
|
||
|
|
# RELAX-NEXT: 0x12 R_LARCH_SUB32 .L2 0x0
|
||
|
|
# RELAX-NEXT: 0x16 R_LARCH_ADD64 .L3 0x0
|
||
|
|
# RELAX-NEXT: 0x16 R_LARCH_SUB64 .L2 0x0
|
||
|
|
+# RELAX-NEXT: 0x1E R_LARCH_ADD8 .L4 0x0
|
||
|
|
+# RELAX-NEXT: 0x1E R_LARCH_SUB8 .L3 0x0
|
||
|
|
+# RELAX-NEXT: 0x1F R_LARCH_ADD16 .L4 0x0
|
||
|
|
+# RELAX-NEXT: 0x1F R_LARCH_SUB16 .L3 0x0
|
||
|
|
+# RELAX-NEXT: 0x21 R_LARCH_ADD32 .L4 0x0
|
||
|
|
+# RELAX-NEXT: 0x21 R_LARCH_SUB32 .L3 0x0
|
||
|
|
+# RELAX-NEXT: 0x25 R_LARCH_ADD64 .L4 0x0
|
||
|
|
+# RELAX-NEXT: 0x25 R_LARCH_SUB64 .L3 0x0
|
||
|
|
# RELAX-NEXT: }
|
||
|
|
# RELAX-NEXT: ]
|
||
|
|
|
||
|
|
# RELAX: Hex dump of section '.data':
|
||
|
|
# RELAX-NEXT: 0x00000000 04040004 00000004 00000000 00000000
|
||
|
|
-# RELAX-NEXT: 0x00000010 00000000 00000000 00000000 00000808
|
||
|
|
-# RELAX-NEXT: 0x00000020 00080000 00080000 00000000 00
|
||
|
|
+# RELAX-NEXT: 0x00000010 00000000 00000000 00000000 00000000
|
||
|
|
+# RELAX-NEXT: 0x00000020 00000000 00000000 00000000 00
|
||
|
|
|
||
|
|
.text
|
||
|
|
.L1:
|
||
|
|
@@ -60,8 +70,6 @@
|
||
|
|
.short .L3 - .L2
|
||
|
|
.word .L3 - .L2
|
||
|
|
.dword .L3 - .L2
|
||
|
|
-## TODO
|
||
|
|
-## With relaxation, emit relocs because la.pcrel is a linker-relaxable inst.
|
||
|
|
.byte .L4 - .L3
|
||
|
|
.short .L4 - .L3
|
||
|
|
.word .L4 - .L3
|
||
|
|
--
|
||
|
|
2.20.1
|
||
|
|
|