ec2f993b84
Update some patch for uadk from mainline. To get more information, please visit the homepage: https://github.comp/Linaro/uadk Signed-off-by: Yang Shen <shenyang39@huawei.com>
70 lines
2.1 KiB
Diff
70 lines
2.1 KiB
Diff
From 2563892aaab90d594b70251253f67efce378c491 Mon Sep 17 00:00:00 2001
|
|
From: Wenkai Lin <linwenkai6@hisilicon.com>
|
|
Date: Sat, 23 Jul 2022 16:50:26 +0800
|
|
Subject: [PATCH 159/183] uadk: fix cqe phase
|
|
|
|
1.Use explicit members from struct cqe is better
|
|
2.Use le16_to_cpu to process a __le16 data
|
|
|
|
This changes sync from kernel patch:
|
|
|
|
crypto: hisilicon - fix endianness verification problem of QM
|
|
|
|
Signed-off-by: Wenkai Lin <linwenkai6@hisilicon.com>
|
|
---
|
|
drv/hisi_qm_udrv.c | 5 +++--
|
|
v1/drv/hisi_qm_udrv.h | 7 ++++---
|
|
2 files changed, 7 insertions(+), 5 deletions(-)
|
|
|
|
diff --git a/drv/hisi_qm_udrv.c b/drv/hisi_qm_udrv.c
|
|
index da756c4..39c99d1 100644
|
|
--- a/drv/hisi_qm_udrv.c
|
|
+++ b/drv/hisi_qm_udrv.c
|
|
@@ -1,6 +1,7 @@
|
|
/* SPDX-License-Identifier: Apache-2.0 */
|
|
/* Copyright 2020-2021 Huawei Technologies Co.,Ltd. All rights reserved. */
|
|
|
|
+#include <asm/byteorder.h>
|
|
#include <limits.h>
|
|
#include <stdlib.h>
|
|
#include <string.h>
|
|
@@ -19,8 +20,8 @@
|
|
#define QM_DBELL_SQN_MASK 0x3ff
|
|
#define QM_DBELL_CMD_MASK 0xf
|
|
#define QM_Q_DEPTH 1024
|
|
-#define CQE_PHASE(cq) (((*((__u32 *)(cq) + 3)) >> 16) & 0x1)
|
|
-#define CQE_SQ_HEAD_INDEX(cq) ((*((__u32 *)(cq) + 2)) & 0xffff)
|
|
+#define CQE_PHASE(cq) (__le16_to_cpu((cq)->w7) & 0x1)
|
|
+#define CQE_SQ_HEAD_INDEX(cq) (__le16_to_cpu((cq)->sq_head) & 0xffff)
|
|
#define VERSION_ID_SHIFT 9
|
|
|
|
#define UACCE_CMD_QM_SET_QP_CTX _IOWR('H', 10, struct hisi_qp_ctx)
|
|
diff --git a/v1/drv/hisi_qm_udrv.h b/v1/drv/hisi_qm_udrv.h
|
|
index 588da00..0d40d86 100644
|
|
--- a/v1/drv/hisi_qm_udrv.h
|
|
+++ b/v1/drv/hisi_qm_udrv.h
|
|
@@ -17,6 +17,7 @@
|
|
#ifndef __HISI_QM_DRV_H__
|
|
#define __HISI_QM_DRV_H__
|
|
|
|
+#include <asm/byteorder.h>
|
|
#include <linux/types.h>
|
|
#include "config.h"
|
|
#include "v1/wd.h"
|
|
@@ -69,9 +70,9 @@
|
|
|
|
|
|
/* cqe shift */
|
|
-#define CQE_PHASE(cq) (((*((__u32 *)(cq) + 3)) >> 16) & 0x1)
|
|
-#define CQE_SQ_NUM(cq) ((*((__u32 *)(cq) + 2)) >> 16)
|
|
-#define CQE_SQ_HEAD_INDEX(cq) ((*((__u32 *)(cq) + 2)) & 0xffff)
|
|
+#define CQE_PHASE(cq) (__le16_to_cpu((cq)->w7) & 0x1)
|
|
+#define CQE_SQ_NUM(cq) __le16_to_cpu((cq)->sq_num)
|
|
+#define CQE_SQ_HEAD_INDEX(cq) (__le16_to_cpu((cq)->sq_head) & 0xffff)
|
|
|
|
/* wd sgl len */
|
|
#define WD_SGL_PAD0_LEN 2
|
|
--
|
|
2.27.0
|
|
|