116 lines
3.8 KiB
Diff
116 lines
3.8 KiB
Diff
From ace1da03900d04a1e14d61200a89c539ff78856d Mon Sep 17 00:00:00 2001
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From: Wenkai Lin <linwenkai6@hisilicon.com>
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Date: Fri, 29 Mar 2024 17:02:23 +0800
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Subject: [PATCH 51/52] uadk: drv_hisi - optimize qm recv function
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Ensure that the value written by the hardware is
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read from the memory each time, reduce the number
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of packet receiving times by half.
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Also sqe address is only need calculated when packets
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are received.
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Signed-off-by: Wenkai Lin <linwenkai6@hisilicon.com>
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Signed-off-by: Qi Tao <taoqi10@huawei.com>
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---
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drv/hisi_qm_udrv.c | 45 +++++++++++++++++++++++----------------------
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1 file changed, 23 insertions(+), 22 deletions(-)
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diff --git a/drv/hisi_qm_udrv.c b/drv/hisi_qm_udrv.c
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index d8b5271..304764e 100644
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--- a/drv/hisi_qm_udrv.c
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+++ b/drv/hisi_qm_udrv.c
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@@ -21,8 +21,8 @@
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#define QM_DBELL_SQN_MASK 0x3ff
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#define QM_DBELL_CMD_MASK 0xf
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#define QM_Q_DEPTH 1024
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-#define CQE_PHASE(cq) (__le16_to_cpu((cq)->w7) & 0x1)
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-#define CQE_SQ_HEAD_INDEX(cq) (__le16_to_cpu((cq)->sq_head) & 0xffff)
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+#define CQE_PHASE(cqe) (__le16_to_cpu((cqe)->w7) & 0x1)
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+#define CQE_SQ_HEAD_INDEX(cqe) (__le16_to_cpu((cqe)->sq_head) & 0xffff)
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#define VERSION_ID_SHIFT 9
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#define UACCE_CMD_QM_SET_QP_CTX _IOWR('H', 10, struct hisi_qp_ctx)
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@@ -505,32 +505,33 @@ int hisi_qm_send(handle_t h_qp, const void *req, __u16 expect, __u16 *count)
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return 0;
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}
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-static int hisi_qm_recv_single(struct hisi_qm_queue_info *q_info, void *resp)
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+static int hisi_qm_recv_single(struct hisi_qm_queue_info *q_info, handle_t h_ctx,
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+ void *resp, __u16 idx)
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{
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- struct hisi_qp *qp = container_of(q_info, struct hisi_qp, q_info);
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+ __u16 i, j, cqe_phase;
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struct cqe *cqe;
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- __u16 i, j;
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pthread_spin_lock(&q_info->rv_lock);
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i = q_info->cq_head_index;
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cqe = q_info->cq_base + i * sizeof(struct cqe);
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+ cqe_phase = CQE_PHASE(cqe);
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+ /* Use dsb to read from memory and improve the receiving efficiency. */
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+ rmb();
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- if (q_info->cqc_phase == CQE_PHASE(cqe)) {
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- /* Make sure cqe valid bit is set */
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- rmb();
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- j = CQE_SQ_HEAD_INDEX(cqe);
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- if (unlikely(j >= q_info->sq_depth)) {
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- pthread_spin_unlock(&q_info->rv_lock);
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- WD_DEV_ERR(qp->h_ctx, "CQE_SQ_HEAD_INDEX(%u) error!\n", j);
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- return -WD_EIO;
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- }
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- memcpy(resp, (void *)((uintptr_t)q_info->sq_base +
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- j * q_info->sqe_size), q_info->sqe_size);
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- } else {
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+ if (q_info->cqc_phase != cqe_phase) {
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pthread_spin_unlock(&q_info->rv_lock);
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return -WD_EAGAIN;
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}
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+ j = CQE_SQ_HEAD_INDEX(cqe);
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+ if (unlikely(j >= q_info->sq_depth)) {
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+ pthread_spin_unlock(&q_info->rv_lock);
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+ WD_DEV_ERR(h_ctx, "CQE_SQ_HEAD_INDEX(%u) error!\n", j);
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+ return -WD_EIO;
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+ }
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+ memcpy((void *)((uintptr_t)resp + idx * q_info->sqe_size),
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+ (void *)((uintptr_t)q_info->sq_base + j * q_info->sqe_size), q_info->sqe_size);
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+
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if (i == q_info->cq_depth - 1) {
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q_info->cqc_phase = !(q_info->cqc_phase);
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i = 0;
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@@ -544,7 +545,7 @@ static int hisi_qm_recv_single(struct hisi_qm_queue_info *q_info, void *resp)
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*/
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if (unlikely(wd_ioread32(q_info->ds_rx_base) == 1)) {
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pthread_spin_unlock(&q_info->rv_lock);
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- WD_DEV_ERR(qp->h_ctx, "wd queue hw error happened after qm receive!\n");
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+ WD_DEV_ERR(h_ctx, "wd queue hw error happened before qm receive!\n");
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return -WD_HW_EACCESS;
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}
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@@ -565,8 +566,9 @@ int hisi_qm_recv(handle_t h_qp, void *resp, __u16 expect, __u16 *count)
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{
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struct hisi_qp *qp = (struct hisi_qp *)h_qp;
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struct hisi_qm_queue_info *q_info;
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- int recv_num = 0;
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- int i, ret, offset;
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+ __u16 recv_num = 0;
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+ __u16 i;
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+ int ret;
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if (unlikely(!resp || !qp || !count))
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return -WD_EINVAL;
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@@ -581,8 +583,7 @@ int hisi_qm_recv(handle_t h_qp, void *resp, __u16 expect, __u16 *count)
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}
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for (i = 0; i < expect; i++) {
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- offset = i * q_info->sqe_size;
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- ret = hisi_qm_recv_single(q_info, resp + offset);
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+ ret = hisi_qm_recv_single(q_info, qp->h_ctx, resp, i);
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if (ret)
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break;
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recv_num++;
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--
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2.25.1
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